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* MIPS: lantiq: verbose init of dma coreJohn Crispin2012-11-111-1/+8
| | | | | | | Print the hardware revision and port/channel info when starting the dma core. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4520
* MIPS: lantiq: fix bootselect bits on XRX200 SoCJohn Crispin2012-11-111-7/+15
| | | | | | | | The XRX200 SoC family has a different register layout for reading the boot selection bits. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4519
* MIPS: lantiq: unbreak devicetree initJohn Crispin2012-11-111-4/+1
| | | | | | | | | The bootmem was incorrectly freed resulting in lots of dangling pointers. Additionally we should use of_platform_populate() as the Documentaion tells us to do so. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4518
* MIPS: Loongson1B: Fix a typoKelvin Cheung2012-11-091-1/+1
| | | | | | | | Fix a typo in the code. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4434 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Loongson1B: Update stmmac_mdio_bus_dataKelvin Cheung2012-11-091-1/+0
| | | | | | | | Update stmmac_mdio_bus_data accordingly due to the upstream change. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4433 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Loongson1B: improve ls1x_serial_setup()Kelvin Cheung2012-11-093-9/+7
| | | | | | | | Improve ls1x_serial_setup(). Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4432 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Loongson1B: use common clock infrastructure instead of private APIsKelvin Cheung2012-11-094-159/+8
| | | | | | | | | | | | Use common clock infrastructure instead of private APIs. 1. Enable COMMON_CLK in the Kconfig. 2. Remove private clock APIs, which are replaced by the code in drivers/clk/clk-ls1x.c. 3. Modify header file for drivers/clk/clk-ls1x.c. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4431 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Support for XLR/XLS Fast Message NetworkGanesan Ramalingam2012-11-0912-12/+1020
| | | | | | | | | | | | | | | | | | | | On XLR/XLS, the cpu cores communicate with fast on-chip devices (e.g. network accelerator, security engine etc.) using the Fast Messaging Network(FMN). The FMN queues and credits needs to be configured and intialized before it can be used. The co-processor 2 on XLR/XLS CPU cores has registers for FMN access, and the XLR/XLS has custom instructions for sending and loading messages. The FMN can deliver also per-cpu interrupts when messages are available at the CPU. This patch adds FMN initialization, adds interrupt setup and handling, and also provides support for sending and receiving FMN messages. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4468 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: PIC IRQ handling update for multi-chipJayachandran C2012-11-095-115/+103
| | | | | | | | | | | | Create struct nlm_pic_irq for interrupts handled by the PIC. This simplifies IRQ handling for multi-SoC as well as the single SoC cases. Also split the setup of percpu and PIC interrupts so that we can configure the PIC interrupts for every node. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4467 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Make number of nodes configurableJayachandran C2012-11-094-5/+90
| | | | | | | | | | There can be 1, 2 or 4 SoCs(nodes) in a multi-chip XLP board. Add an option for multi-chip boards in case of XLP, and make the number of nodes configurable. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4470 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Support for multi-chip configurationJayachandran C2012-11-0912-86/+176
| | | | | | | | | | | | Upto 4 Netlogic XLP SoCs can be connected over ICI links to form a coherent multi-node system. Each SoC has its own set of on-chip devices including PIC. To support this, add a per SoC stucture and use it for the PIC and SYS block addresses instead of using global variables. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4469 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Move from u32 cpumask to cpumask_tJayachandran C2012-11-096-55/+86
| | | | | | | | | | Initial code to support more than 32 cpus. The platform CPU mask is updated from 32-bit mask to cpumask_t. Convert places that use cpu_/cpus_ functions to use cpumask_* functions. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4464 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Update PIC access functionsJayachandran C2012-11-091-33/+7
| | | | | | | | | | Remove unused and trivial PIC accesss functions, update nlm_pic_send_ipi() and nlm_set_irt_to_cpu() to use similar logic, and use correct type for reg in nlm_pic_disable_irt(). Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4463 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Pass cpuid to early_init_secondaryJayachandran C2012-11-092-2/+4
| | | | | | | | | The cpuid was not passed into early_init_secondary even though the comment indicated that it will be. Fix this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4458 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Fix interrupt table entry initJayachandran C2012-11-091-1/+1
| | | | | | | | | Used the hardware thread id passed in while writing to IRT in nlm_pic_init_irt() Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4465 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Fix DMA zone selection for 64-bitJayachandran C2012-11-091-2/+2
| | | | | | | | | | Fix Kconfig for both XLR and XLP to select ZONE_DMA32 (instead of ZONE_DMA) in case of 64-bit compilation. This can be used for devices that can only do DMA to 32-bit address. ZONE_DMA is not useful on XLR or XLP. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4466 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Move fdt init to plat_mem_setupJayachandran C2012-11-091-13/+14
| | | | | | | | | At this point early printk is available, so debugging device tree issues is easier. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4460 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: Enable SUE bit in coresJayachandran C2012-11-091-1/+1
| | | | | | | | | | Enable Speculative Unmap Enable bit, which will enable speculative L2 cache requests for unmapped memory. This should give better performance for kernel code/data which is in KSEG0 Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4461 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Netlogic: select MIPSR2 for XLPJayachandran C2012-11-091-1/+2
| | | | | | | | | | | This allows us to use the r2 optimized code from kernel headers while compilation. Disable PGD_C0_CONTEXT option for XLP, which does not work. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4456 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: perf: Add XLP support for hardware perf.Zi Shen Lim2012-11-092-1/+125
| | | | | | | | | | Add support for XLP performance counters register in perf. Update mips/Kconfig so that perf events can be selected for XLP. Signed-off-by: Zi Shen Lim <zlim@netlogicmicro.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4457 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: oprofile: Support for XLR/XLS processorsMadhusudan Bhat2012-11-093-0/+31
| | | | | | | | | | | | | | | Add support for XLR and XLS processors in MIPS Oprofile code. These processors are multi-threaded and have two counters per core. Each counter can track either all the events in the core (global mode), or events in just one thread. We use the counters in the global mode, and use only the first thread in each core to handle the configuration etc. Signed-off-by: Madhusudan Bhat <mbhat@netlogicmicro.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4471 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM63XX: move nvram functions into their own fileJonas Gorski2012-11-095-80/+154
| | | | | | | | | Refactor nvram related functions into its own unit for easier expansion and exposure of the values to other drivers. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4516 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM63XX: use the new reset helperJonas Gorski2012-11-092-27/+11
| | | | | | | | Use the new reset helper where appropriate. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4453 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM63XX: add core reset helperJonas Gorski2012-11-093-3/+247
| | | | | | | | Add a reset helper for resetting the different cores. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4455 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM63XX: add softreset register description for BCM6358Jonas Gorski2012-11-091-0/+10
| | | | | | | | The softreset register description for BCM6358 was missing, so add it. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4454 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM63XX: add and use a clock for PCIeJonas Gorski2012-11-092-5/+25
| | | | | | | | | | Add a PCIe clock and use that instead of directly touching the clock control register. While at it, fail if there is no such clock. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4452 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM47xx: sprom: read values without prefix as fallbackHauke Mehrtens2012-11-093-332/+449
| | | | | | | | | | | | | | | There are bcma based devices like the Linksys E2000 out there, which do have one ieee80211 core, but no PCIe core and they are using no prefixes for the sprom. In addition some values like boardtype are stored without a prefix for the main SoC chip also when they have an additional PCIe wifi chip with an own boardtype var on some devices. The Ethernet addresses are now also read out correctly without a prefix so calling bcm47xx_fill_sprom_ethernet is not needed any more. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4364 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM47XX: read sprom without prefix if no ieee80211 coreHauke Mehrtens2012-11-091-0/+2
| | | | | | | | | If there is no ieee80211 core on the devices like on the BCM4706 read out the sprom and the other data without using a prefix. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4361 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM47xx: read out full board dataHauke Mehrtens2012-11-091-20/+14
| | | | | | | | | | | Read out the full board data independently of the sprom version. Now we also get the full boardflags and so on if sromrev is not set and our code would assume a rev 1 device. When a nvram option is not set because it is not there this is no problem. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4363 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM47XX: improve memory size detectionHauke Mehrtens2012-11-091-4/+6
| | | | | | | | | | | | | | The memory size is detected by finding a place where it repeats in memory. Currently we are just checking when the function prom_init is seen again, but it is better to check for a bigger part of the memory to decrease the chance of wrong results. This should fix a problem we saw in OpenWrt, where the detected available memory decreed on some devices when doing a soft reboot. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4362 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM47XX: ignore last memory pageHauke Mehrtens2012-11-091-0/+10
| | | | | | | | | | Ignoring the last page when ddr size is 128M. Cached accesses to last page is causing the processor to prefetch using address above 128M stepping out of the ddr address space. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4365 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Move processing of coherency kernel parameters earlierShane McDonald2012-11-091-4/+4
| | | | | | | | | | | | | | | | | | Commit 97ce2c88f9ad42e3c60a9beb9fca87abf3639faa (jump-label: initialize jump-label subsystem much earlier) caused MIPS to break, so this was resolved with commit 6650df3c380e0db558dbfec63ed860402c6afb2a (MIPS: Move cache setup to setup_arch().). Unfortunately, after this commit, the coherency kernel parameters, cca and coherentio, are no longer processed before their values are used. This patch fixes this problem by marking them as early_param, which results in them being processed before they are needed. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> Acked-by: David Daney <david.daney@cavium.com> Cc: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/3961 Signed-off-by: John Crispin <blogic@openwrt.org>
* mips/octeon: 16-Bit NOR flash was not being detected during bootCharles Hardin2012-11-091-1/+2
| | | | | | | | | | | | | | The cavium code assumed that all NOR on the boot bus was an 8-bit NOR part and hardcoded the bankwidth. The simple solution was to add the code that queries the configuration register for the width of the bus that has been hardware strapped to the Cavium. This allows both 8-bit and 16-bit parts to be discovered during boot. Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Charles Hardin <ckhardin@exablox.com> Patchwork: http://patchwork.linux-mips.org/patch/4323 Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: tlbex: Fix section mismatchesKevin Cernekee2012-11-091-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The new functions introduced in commit 02a5417751 (MIPS: tlbex: Deal with re-definition of label) should be marked __cpuinit, to eliminate a warning that can pop up when CONFIG_EXPORT_UASM is disabled: LD arch/mips/mm/built-in.o WARNING: arch/mips/mm/built-in.o(.text+0x2a4c): Section mismatch in reference from the function uasm_bgezl_hazard() to the function .cpuinit.text:uasm_il_bgezl() The function uasm_bgezl_hazard() references the function __cpuinit uasm_il_bgezl(). This is often because uasm_bgezl_hazard lacks a __cpuinit annotation or the annotation of uasm_il_bgezl is wrong. WARNING: arch/mips/mm/built-in.o(.text+0x2a68): Section mismatch in reference from the function uasm_bgezl_label() to the function .cpuinit.text:uasm_build_label() The function uasm_bgezl_label() references the function __cpuinit uasm_build_label(). This is often because uasm_bgezl_label lacks a __cpuinit annotation or the annotation of uasm_build_label is wrong. (This warning might not occur if the function was inlined.) Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4517 Signed-off-by: John Crispin <blogic@openwrt.org>
* Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2012-11-077-29/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull arm fixes from Russell King: "Not much here again. The two most notable things here are the sched_clock() fix, which was causing problems with the scheduling of threaded IRQs after a suspend event, and the vfp fix, which afaik has only been seen on some older OMAP boards. Nevertheless, both are fairly important fixes." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7569/1: mm: uninitialized warning corrections ARM: 7567/1: io: avoid GCC's offsettable addressing modes for halfword accesses ARM: 7566/1: vfp: fix save and restore when running on pre-VFPv3 and CONFIG_VFPv3 set ARM: 7565/1: sched: stop sched_clock() during suspend
| * ARM: 7569/1: mm: uninitialized warning correctionsviresh kumar2012-11-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | The variables here are really not used uninitialized. arch/arm/mm/alignment.c: In function 'do_alignment': arch/arm/mm/alignment.c:327:15: warning: 'offset.un' may be used uninitialized in this function [-Wmaybe-uninitialized] arch/arm/mm/alignment.c:748:21: note: 'offset.un' was declared here Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7567/1: io: avoid GCC's offsettable addressing modes for halfword accessesWill Deacon2012-10-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the 'o' memory constraint in inline assembly can result in GCC generating invalid immediate offsets for memory access instructions with reduced addressing capabilities (i.e. smaller than 12-bit immediate offsets): http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54983 As there is no constraint to specify the exact addressing mode we need, fallback to using 'Q' exclusively for halfword I/O accesses. This may emit an additional add instruction (using an extra register) in order to construct the address but it will always be accepted by GAS. Reported-by: Bastian Hecht <hechtb@googlemail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7566/1: vfp: fix save and restore when running on pre-VFPv3 and ↵Paul Walmsley2012-10-293-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_VFPv3 set After commit 846a136881b8f73c1f74250bf6acfaa309cab1f2 ("ARM: vfp: fix saving d16-d31 vfp registers on v6+ kernels"), the OMAP 2430SDP board started crashing during boot with omap2plus_defconfig: [ 3.875122] mmcblk0: mmc0:e624 SD04G 3.69 GiB [ 3.915954] mmcblk0: p1 [ 4.086639] Internal error: Oops - undefined instruction: 0 [#1] SMP ARM [ 4.093719] Modules linked in: [ 4.096954] CPU: 0 Not tainted (3.6.0-02232-g759e00b #570) [ 4.103149] PC is at vfp_reload_hw+0x1c/0x44 [ 4.107666] LR is at __und_usr_fault_32+0x0/0x8 It turns out that the context save/restore fix unmasked a latent bug in commit 5aaf254409f8d58229107b59507a8235b715a960 ("ARM: 6203/1: Make VFPv3 usable on ARMv6"). When CONFIG_VFPv3 is set, but the kernel is booted on a pre-VFPv3 core, the code attempts to save and restore the d16-d31 VFP registers. These are only present on non-D16 VFPv3+, so this results in an undefined instruction exception. The code didn't crash before commit 846a136 because the save and restore code was only touching d0-d15, present on all VFP. Fix by implementing a request from Russell King to add a new HWCAP flag that affirmatively indicates the presence of the d16-d31 registers: http://marc.info/?l=linux-arm-kernel&m=135013547905283&w=2 and some feedback from Måns to clarify the name of the HWCAP flag. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Dave Martin <dave.martin@linaro.org> Cc: Måns Rullgård <mans.rullgard@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7565/1: sched: stop sched_clock() during suspendFelipe Balbi 22012-10-292-16/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The scheduler imposes a requirement to sched_clock() which is to stop the clock during suspend, if we don't do that any RT thread will be rescheduled in the future which might cause any sort of problems. This became an issue on OMAP when we converted omap-i2c.c to use threaded IRQs, it turned out that depending on how much time we spent on suspend, the I2C IRQ thread would end up being rescheduled so far in the future that I2C transfers would timeout and, because omap_hsmmc depends on an I2C-connected device to detect if an MMC card is inserted in the slot, our rootfs would just vanish. arch/arm/kernel/sched_clock.c already had an optional implementation (sched_clock_needs_suspend()) which would handle scheduler's requirement properly, what this patch does is simply to make that implementation non-optional. Note that this has the side-effect that printk timings won't reflect the actual time spent on suspend so other methods to measure that will have to be used. This has been tested with beagleboard XM (OMAP3630) and pandaboard rev A3 (OMAP4430). Suspend to RAM is now working after this patch. Thanks to Kevin Hilman for helping out with debugging. Acked-by: Kevin Hilman <khilman@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge tag 'frv-fixes-20121102' of ↵Linus Torvalds2012-11-026-32/+14
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-frv Pull FRV fixes from David Howells: "A collection of small fixes for the FRV architecture." * tag 'frv-fixes-20121102' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-frv: frv: fix the broken preempt frv: switch to saner kernel_execve() semantics FRV: Fix the new-style kernel_thread() stuff FRV: Fix the preemption handling FRV: gcc-4.1.2 also inlines weak functions FRV: Don't objcopy the GNU build_id note FRV: Add missing linux/export.h #inclusions
| * | frv: fix the broken preemptAl Viro2012-11-021-20/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Just get %icc2 into the state we would have after local_irq_disable() and physical IRQ having happened since then. Then we can simply use preempt_schedule_irq() and be done with the whole mess. Acked-by: David Howells <dhowells@redhat.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
| * | frv: switch to saner kernel_execve() semanticsAl Viro2012-11-023-6/+1
| | | | | | | | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
| * | FRV: Fix the new-style kernel_thread() stuffDavid Howells2012-11-021-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel_thread() changes for FRV don't work, and FRV fails to boot, starting with: commit 02ce496f152df87be081a64796498942c433a2fd Author: Al Viro <viro@zeniv.linux.org.uk> Date: Tue Sep 18 22:18:51 2012 -0400 Subject: frv: split ret_from_fork, simplify kernel_thread() a lot The problem is that the userspace registers are completely cleared when a kernel thread is created and all subsequent user threads are then copied from that. Unfortunately, however, the TBR and PSR registers are restored from the pt_regs and the values they should be set to are clobbered by the memset. Instead, copy across the old user registers as normal, and then merely alter GR8 and GR9 in it if we're going to execute a kernel thread. Signed-off-by: David Howells <dhowells@redhat.com>
| * | FRV: Fix the preemption handlingDavid Howells2012-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the preemption handling in FRV code where the PREEMPT_ACTIVE value is incorrectly loaded into the threadinfo flags rather than the threadinfo preemption count. Unfortunately, the code cannot be simply converted to use preempt_schedule_irq() as is because FRV uses virtual interrupt disablement to cut down on the cost of actually disabling interrupts and thus local_irq_enable() doesn't actually enable interrupts. Reported-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: David Howells <dhowells@redhat.com> cc: Al Viro <viro@ZenIV.linux.org.uk>
| * | FRV: Don't objcopy the GNU build_id noteDavid Howells2012-11-021-4/+6
| | | | | | | | | | | | | | | | | | | | | Don't let objcopy transfer the GNU build_id note into the loadable image as it is located at address 0 and the image ends up >3G in size. Signed-off-by: David Howells <dhowells@redhat.com>
| * | FRV: Add missing linux/export.h #inclusionsDavid Howells2012-11-021-0/+1
| | | | | | | | | | | | | | | | | | Add missing linux/export.h #inclusions to the FRV arch. Signed-off-by: David Howells <dhowells@redhat.com>
* | | Merge tag 'stable/for-linus-3.7-rc4-tag' of ↵Linus Torvalds2012-11-023-11/+25
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen Pull Xen bugfixes from Konrad Rzeszutek Wilk: - Use appropriate macros instead of hand-rolling our own (ARM). - Fixes if FB/KBD closed unexpectedly. - Fix memory leak in /dev/gntdev ioctl calls. - Fix overflow check in xenbus_file_write. - Document cleanup. - Performance optimization when migrating guests. * tag 'stable/for-linus-3.7-rc4-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen: xen/mmu: Use Xen specific TLB flush instead of the generic one. xen/arm: use the __HVC macro xen/xenbus: fix overflow check in xenbus_file_write() xen-kbdfront: handle backend CLOSED without CLOSING xen-fbfront: handle backend CLOSED without CLOSING xen/gntdev: don't leak memory from IOCTL_GNTDEV_MAP_GRANT_REF x86: remove obsolete comment from asm/xen/hypervisor.h
| * | | xen/mmu: Use Xen specific TLB flush instead of the generic one.Konrad Rzeszutek Wilk2012-10-311-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As Mukesh explained it, the MMUEXT_TLB_FLUSH_ALL allows the hypervisor to do a TLB flush on all active vCPUs. If instead we were using the generic one (which ends up being xen_flush_tlb) we end up making the MMUEXT_TLB_FLUSH_LOCAL hypercall. But before we make that hypercall the kernel will IPI all of the vCPUs (even those that were asleep from the hypervisor perspective). The end result is that we needlessly wake them up and do a TLB flush when we can just let the hypervisor do it correctly. This patch gives around 50% speed improvement when migrating idle guest's from one host to another. Oracle-bug: 14630170 CC: stable@vger.kernel.org Tested-by: Jingjie Jiang <jingjie.jiang@oracle.com> Suggested-by: Mukesh Rathor <mukesh.rathor@oracle.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * | | xen/arm: use the __HVC macroStefano Stabellini2012-10-301-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new __HVC macro in hypercall.S. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * | | x86: remove obsolete comment from asm/xen/hypervisor.hOlaf Hering2012-10-301-1/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Olaf Hering <olaf@aepfle.de> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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