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* Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds2011-01-182-7/+11
|\ | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: Clear irqstack thread_info x86: Make relocatable kernel work with new binutils
| * x86: Clear irqstack thread_infoBrian Gerst2011-01-181-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mathias Merz reported that v2.6.37 failed to boot on his system. Make sure that the thread_info part of the irqstack is initialized to zeroes. Reported-and-Tested-by: Matthias Merz <linux@merz-ka.de> Signed-off-by: Brian Gerst <brgerst@gmail.com> Acked-by: Pekka Enberg <penberg@kernel.org> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> LKML-Reference: <AANLkTimyKXfJ1x8tgwrr1hYnNLrPfgE1NTe4z7L6tUDm@mail.gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: Make relocatable kernel work with new binutilsShaohua Li2011-01-181-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_RELOCATABLE=y option is broken with new binutils, which will make boot panic. According to Lu Hongjiu, the affected binutils are from 2.20.51.0.12 to 2.21.51.0.3, which are release since Oct 22 this year. At least ubuntu 10.10 is using such binutils. See: http://sourceware.org/bugzilla/show_bug.cgi?id=12327 The reason of the boot panic is that we have 'jiffies = jiffies_64;' in vmlinux.lds.S. The jiffies isn't in any section. In kernel build, there is warning saying jiffies is an absolute address and can't be relocatable. At runtime, jiffies will have virtual address 0. Signed-off-by: Shaohua Li<shaohua.li@intel.com> Cc: Lu Hongjiu<hongjiu.lu@intel.com> Cc: Huang Ying <ying.huang@intel.com> Cc: Sam Ravnborg <sam@ravnborg.org> LKML-Reference: <1295312269.1949.725.camel@sli10-conroe> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2011-01-1855-129/+3107
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (26 commits) MIPS: Malta: enable Cirrus FB console MIPS: add CONFIG_VIRTUALIZATION for virtio support MIPS: Implement __read_mostly MIPS: ath79: add common WMAC device for AR913X based boards MIPS: ath79: Add initial support for the Atheros AP81 reference board MIPS: ath79: add common SPI controller device SPI: Add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs MIPS: ath79: add common GPIO buttons device MIPS: ath79: add common watchdog device MIPS: ath79: add common GPIO LEDs device MIPS: ath79: add initial support for the Atheros PB44 reference board MIPS: ath79: utilize the MIPS multi-machine support MIPS: ath79: add GPIOLIB support MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs MIPS: jump label: Add MIPS support. MIPS: Use WARN() in uasm for better diagnostics. MIPS: Optimize TLB handlers for Octeon CPUs MIPS: Add LDX and LWX instructions to uasm. MIPS: Use BBIT instructions in TLB handlers MIPS: Declare uasm bbit0 and bbit1 functions. ...
| * | MIPS: Malta: enable Cirrus FB consoleAurelien Jarno2011-01-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While most users of a physical Malta board are using the serial port as the console, a lot of QEMU users would prefer to interact with a graphical console. Enable the Cirrus FB support in the Malta default configuration to make that possible. Note that the default console will still be the serial port, users have to pass "console=tty0" to the kernel to use the Cirrus FB. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2001/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: add CONFIG_VIRTUALIZATION for virtio supportAurelien Jarno2011-01-181-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_VIRTUALIZATION to the MIPS architecture and include the the virtio code there. Used to enable the virtio drivers under QEMU. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2002/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Implement __read_mostlyDavid Daney2011-01-182-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just do what everyone else is doing by placing __read_mostly things in the .data.read_mostly section. mips_io_port_base can not be read-only (const) and writable (__read_mostly) at the same time. One of them has to go, so I chose to eliminate the __read_mostly. It will still get stuck in a portion of memory that is not adjacent to things that are written, and thus not be on a dirty cache line, for whatever that is worth. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1702/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: add common WMAC device for AR913X based boardsGabor Juhos2011-01-186-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add common platform_device and helper code to make the registration of the built-in wireless MAC easier on the Atheros AR9130/AR9132 based boards. Also register the WMAC device on the AR81 board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org>, Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Add initial support for the Atheros AP81 reference boardGabor Juhos2011-01-184-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1952/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: add common SPI controller deviceGabor Juhos2011-01-186-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several boards are using the built-in SPI controller of the AR71XX/AR724X/AR913X SoCs. This patch adds common platform_device and helper code to register it. Additionally, the patch registers the SPI bus on the PB44 board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1956/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | SPI: Add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCsGabor Juhos2011-01-181-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This patch implements a driver for that. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: spi-devel-general@lists.sourceforge.net Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1960/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: add common GPIO buttons deviceGabor Juhos2011-01-185-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all boards have one or more push buttons connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the buttons on the PB44 board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1954/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: add common watchdog deviceGabor Juhos2011-01-183-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All supported SoCs have a built-in hardware watchdog driver. This patch registers a platform_device for that to make it usable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: add common GPIO LEDs deviceGabor Juhos2011-01-185-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all boards have one or more LEDs connected to GPIO lines. This patch adds common code to register a platform_device for them. The patch also adds support for the LEDs on the PB44 board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1953/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: add initial support for the Atheros PB44 reference boardGabor Juhos2011-01-184-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1950/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: utilize the MIPS multi-machine supportGabor Juhos2011-01-183-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1949/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: add GPIOLIB supportGabor Juhos2011-01-187-2/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements generic GPIO routines for the built-in GPIO controllers of the Atheros AR71XX/AR724X/AR913X SoCs. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1948/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCsGabor Juhos2011-01-1820-0/+1365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: jump label: Add MIPS support.David Daney2011-01-185-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order not to be left behind, we add jump label support for MIPS. Tested on 64-bit big endian (Octeon), and 32-bit little endian (malta/qemu). Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Jason Baron <jbaron@redhat.com> Patchwork: https://patchwork.linux-mips.org/patch/1923/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Use WARN() in uasm for better diagnostics.David Daney2011-01-181-24/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the off chance that uasm ever warns about overflow, there is no way to know what the offending instruction is. Change the printks to WARNs, so we can get a nice stack trace. It has the added benefit of being much more noticeable than the short single line warning message, so is less likely to be ignored. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1905/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Optimize TLB handlers for Octeon CPUsDavid Daney2011-01-181-51/+310
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Octeon can use scratch registers in the TLB handlers. Octeon II can use LDX instructions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1904/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add LDX and LWX instructions to uasm.David Daney2011-01-183-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Needed by Octeon II optimized TLB handlers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Pachwork: https://patchwork.linux-mips.org/patch/1903/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Use BBIT instructions in TLB handlersDavid Daney2011-01-181-29/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they are more efficient than an AND followed by an branch and then restoring the clobbered register. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1873/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Declare uasm bbit0 and bbit1 functions.David Daney2011-01-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | these are already defined, but declaring them allow them to be used outside of uasm.c. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1872/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Use C0_KScratch (if present) to hold PGD pointer.David Daney2011-01-183-18/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Decide at runtime to use either Context or KScratch to hold the PGD pointer. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add DINSM to uasm.David Daney2011-01-182-1/+11
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1875/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Probe for presence of KScratch registers.David Daney2011-01-183-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1877/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add generic support for multiple machines within a single kernelGabor Juhos2011-01-186-1/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a generic solution to support multiple machines based on a given SoC within a single kernel image. It is implemented already for several other architectures but MIPS has no generic support for that yet. [Ralf: This competes with DT but DT is a much more complex solution and this code has been used by OpenWRT for a long time so for now DT is a bad reason to stop the merge but longer term this should be migrated to DT.] Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: kaloz@openwrt.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Use printf extension %pR for struct resourceJoe Perches2011-01-181-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using %pR standardizes the struct resource output. Signed-off-by: Joe Perches <joe@perches.com> To: Jiri Kosina <trivial@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1772/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Sibyte: Use vzalloc in sbbus profilerJoe Perches2011-01-181-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Joe Perches <joe@perches.com> To: Jiri Kosina <trivial@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1756/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | Merge branch 'fixes' of ↵Linus Torvalds2011-01-181-12/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6 * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6: parisc: fix compile breakage caused by inlining maybe_mkwrite parisc : Remove broken line wrapping handling pdc_iodc_print()
| * | | parisc: fix compile breakage caused by inlining maybe_mkwriteJames Bottomley2011-01-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Parisc, we have an include of linux/mm.h inside our asm/pgtable.h, so this patch commit 14fd403f2146f740942d78af4e0ee59396ad8eab Author: Andrea Arcangeli <aarcange@redhat.com> Date: Thu Jan 13 15:46:37 2011 -0800 thp: export maybe_mkwrite Causes us an unsatisfiable use of pte_mkwrite in linux/mm.h The fix is obviously not to include linux/mm.h in our pgtable.h, which unbreaks the build. Signed-off-by: James Bottomley <James.Bottomley@suse.de>
| * | | parisc : Remove broken line wrapping handling pdc_iodc_print()Guy Martin2011-01-151-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the broken line wrapping handling in pdc_iodc_print(). It is broken in 3 ways : - It doesn't keep track of the current screen position, it just assumes that the new buffer will be printed at the begining of the screen. - It doesn't take in account that non printable characters won't increase the current position on the screen. - And last but not least, it triggers a kernel panic if a backspace is the first char in the provided buffer : Backtrace: [<0000000040128ec4>] pdc_console_write+0x44/0x78 [<0000000040128f18>] pdc_console_tty_write+0x20/0x38 [<000000004032f1ac>] n_tty_write+0x2a4/0x550 [<000000004032b158>] tty_write+0x1e0/0x2d8 [<00000000401bb420>] vfs_write+0xb8/0x188 [<00000000401bb630>] sys_write+0x68/0xb8 [<0000000040104eb8>] syscall_exit+0x0/0x14 Most terminals handle the line wrapping just fine. I've confirmed that it works correctly on a C8000 with both vga and serial output. Signed-off-by: Guy Martin <gmsoft@tuxicoman.be> Cc: Stable Tree <stable@kernel.org> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
* | | | Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblazeLinus Torvalds2011-01-182-2/+5
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Fix asm/pgtable.h microblaze: Fix missing pagemap.h
| * | | | microblaze: Fix asm/pgtable.hMichal Simek2011-01-161-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function ptep_test_and_clear_young have had wrong the first argument. It is also necessary to add __HAVE macros for ptep_test_and_clear_young and ptep_get_and_clear functions. Error log: In file included from linux/arch/microblaze/include/asm/pgtable.h:570, from arch/microblaze/mm/pgtable.c:35: include/asm-generic/pgtable.h:23: error: conflicting types for 'ptep_test_and_clear_young' linux/arch/microblaze/include/asm/pgtable.h:449: error: previous definition of 'ptep_test_and_clear_young' was here include/asm-generic/pgtable.h:73: error: redefinition of 'ptep_get_and_clear' linux/arch/microblaze/include/asm/pgtable.h:462: error: previous definition of 'ptep_get_and_clear' was here Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | | microblaze: Fix missing pagemap.hMichal Simek2011-01-161-0/+1
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing linux/pagemap.h to solve compilation error. Error log: In file included from linux/arch/microblaze/include/asm/tlb.h:17, from mm/pgtable-generic.c:9: include/asm-generic/tlb.h: In function 'tlb_flush_mmu': include/asm-generic/tlb.h:76: error: implicit declaration of function 'release_pages' include/asm-generic/tlb.h: In function 'tlb_remove_page': include/asm-generic/tlb.h:105: error: implicit declaration of function 'page_cache_release' Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | | Merge branch 'for-linus' of ↵Linus Torvalds2011-01-1838-623/+727
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (25 commits) m68knommu: fix broken setting of irq_chip and handler m68knommu: switch to using -mcpu= flags for ColdFire targets m68knommu: arch/m68knommu/Kconfig whitespace cleanup m68knommu: create optimal separate instruction and data cache for ColdFire m68knommu: support ColdFire caches that do copyback and write-through m68knommu: support version 2 ColdFire split cache m68knommu: make cache push code ColdFire generic m68knommu: clean up ColdFire cache control code m68knommu: move inclusion of ColdFire v4 cache registers m68knommu: merge bit definitions for version 3 ColdFire cache controller m68knommu: create bit definitions for the version 2 ColdFire cache controller m68knommu: remove empty __iounmap() it is no used m68knommu: remove kernel_map() code, it is not used m68knommu: remove do_page_fault(), it is not used m68knommu: use user stack pointer hardware on some ColdFire cores m68knommu: remove command line printing DEBUG m68knommu: remove fasthandler interrupt code m68knommu: move UART addressing to part specific includes m68knommu: fix clock rate value reported for ColdFire 54xx parts m68knommu: move ColdFire CPU names into their headers ...
| * | | | m68knommu: fix broken setting of irq_chip and handlerGreg Ungerer2011-01-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix compile error, by using correct loop variable: arch/m68knommu/platform/68328/ints.c: In function ‘init_IRQ’: arch/m68knommu/platform/68328/ints.c:182: error: ‘irq’ undeclared (first use in this function) arch/m68knommu/platform/68328/ints.c:182: error: (Each undeclared identifier is reported only once arch/m68knommu/platform/68328/ints.c:182: error: for each function it appears in.) Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: switch to using -mcpu= flags for ColdFire targetsGreg Ungerer2011-01-051-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gcc has deprecated the use of the following ColdFire cpu options: -m5206e, -m528x, -m5307 and -m5407. In there place we should use the equivilent -mcpu= option and setting. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: arch/m68knommu/Kconfig whitespace cleanupPhilippe De Muyter2011-01-051-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace 8 spaces, or even 7, by TAB at begin of lines. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: create optimal separate instruction and data cache for ColdFireGreg Ungerer2011-01-054-20/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create separate functions to deal with instruction and data cache flushing. This way we can optimize them for the vairous cache types and arrangements used across the ColdFire family. For example the unified caches in the version 3 cores means we don't need to flush the instruction cache. For the version 2 cores that do not do data cacheing (or where we choose instruction cache only) we don't need to do any data flushing. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: support ColdFire caches that do copyback and write-throughGreg Ungerer2011-01-053-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The version 3 and version 4 ColdFire cache controllers support both write-through and copy-back modes on the data cache. Allow for Kconfig time configuration of this, and set the cache mode appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: support version 2 ColdFire split cacheGreg Ungerer2011-01-052-14/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newer version 2 ColdFire CPU cores support a configurable cache arrangement. The cache memory can be used as all instruction cache, all data cache, or split in half for both instruction and data caching. Support this setup via a Kconfig time menu that allows a kernel builder to choose the arrangement they want to use. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: make cache push code ColdFire genericGreg Ungerer2011-01-054-39/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the code to push cache lines is only available to version 4 cores. Version 3 cores may also need to use this if we support copy- back caches on them. Move this code to make it more generic, and useful for all version ColdFire cores. With this in place we can now have a single cache_flush_all() code path that does all the right things on all version cores. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: clean up ColdFire cache control codeGreg Ungerer2011-01-056-192/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cache control code for the ColdFire CPU's is a big ugly mess of "#ifdef"ery liberally coated with bit constants. Clean it up. The cache controllers in the various ColdFire parts are actually quite similar. Just differing in some bit flags and options supported. Using the header defines now in place it is pretty easy to factor out the small differences and use common setup and flush/invalidate code. I have preserved the cache setups as they where in the old code (except where obviously wrong - like in the case of the 5249). Following from this it should be easy now to extend the possible setups used on the CACHE controllers that support split cacheing or copy-back or write through options. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: move inclusion of ColdFire v4 cache registersGreg Ungerer2011-01-054-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the inclusion of the version 4 cache controller registers so that it is with all the other register bit flag definitions. This makes it consistent with the other version core inclusion points, and means we don't need "#ifdef"ery in odd-ball places for these definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: merge bit definitions for version 3 ColdFire cache controllerGreg Ungerer2011-01-053-54/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All version 3 based ColdFire CPU cores have a similar cache controller. Merge all the exitsing definitions into a single file, and make them similar in style and naming to the existing version 2 and version 4 cache controller definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: create bit definitions for the version 2 ColdFire cache controllerGreg Ungerer2011-01-058-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: remove empty __iounmap() it is no usedGreg Ungerer2011-01-052-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The empty __iounmap() function is not used on m68knommu at all. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | | m68knommu: remove kernel_map() code, it is not usedGreg Ungerer2011-01-052-34/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel_map() functions is not used anywhere, remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 00:23:34 +0000