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* ARM64 / ACPI: fix usage of acpi_map_gic_cpu_interfaceWill Deacon2015-03-261-6/+5
| | | | | | | | | | | acpi_parse_gic_cpu_interface calls acpi_map_gic_cpu_interface by both passing a 32-bit value in the u8 enabled parameter and then subsequently ignoring its return value. Sort it out. Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64: kernel: acpi: honour acpi=force command line parameterLorenzo Pieralisi2015-03-263-8/+13
| | | | | | | | | | | | | | | | | If acpi=force is passed on the command line, it forces ACPI to be the only available boot method, hence it must be left enabled even if the initialization and sanity checks on ACPI tables fails. This patch refactors ACPI initialization to prevent disabling ACPI if acpi=force is passed on the command line. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Hanjun Guo <hanjun.guo@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64: kernel: acpi: refactor ACPI tables init and checksLorenzo Pieralisi2015-03-261-36/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current ACPI init code on ARM64 relies on acpi_table_parse() API to check if the FADT is present and to carry out sanity checks on that. The handler passed to the acpi_table_parse() function and used to carry out the parsing on the requested table returns a value that is ignored by the acpi_table_parse() function, so it is not possible to propagate errors back to the acpi_table_parse() caller through the handler. This forces ARM64 ACPI init code to have disable_acpi() calls scattered all over the place that makes code unwieldy and not easy to follow. This patch refactors the ARM64 ACPI init code, by creating a self-contained function (ie acpi_fadt_sanity_check()) that carries out the required checks on FADT and returns an adequate return value to the caller. This allows creating a common error path that disables ACPI and makes code more readable and easy to parse and change were further checks FADT to be added in the future. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64: kernel: psci: let ACPI probe PSCI versionLorenzo Pieralisi2015-03-261-3/+1
| | | | | | | | | | | | | | PSCI v0.2+ allows the kernel to probe the PSCI firmware version. This patch replaces the default initialization of PSCI v0.2+ functions with code that allows probing PSCI firmware version and initializes PSCI functions accordingly. Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64: kernel: psci: factor out probe functionLorenzo Pieralisi2015-03-261-16/+34
| | | | | | | | | | | | | | | | | PSCI v0.2+ versions provide a specific PSCI call (PSCI_VERSION) to detect the PSCI version at run-time. Current PSCI v0.2 init code carries out the version probing in the PSCI 0.2 DT init function, but the version probing does not depend on DT so it can be factored out in order to make it available to other boot mechanisms (ie ACPI) to reuse. The psci_probe() probing function can be easily extended to add detection and initialization of PSCI functions defined in PSCI versions >0.2. Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ACPI: move arm64 GSI IRQ model to generic GSI IRQ layerLorenzo Pieralisi2015-03-262-73/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code deployed to implement GSI linux IRQ numbers mapping on arm64 turns out to be generic enough so that it can be moved to ACPI core code along with its respective config option ACPI_GENERIC_GSI selectable on architectures that can reuse the same code. Current ACPI IRQ mapping code is not integrated in the kernel IRQ domain infrastructure, in particular there is no way to look-up the IRQ domain associated with a particular interrupt controller, so this first version of GSI generic code carries out the GSI<->IRQ mapping relying on the IRQ default domain which is supposed to be always set on a specific architecture in case the domain structure passed to irq_create/find_mapping() functions is missing. This patch moves the arm64 acpi functions that implement the gsi mappings: acpi_gsi_to_irq() acpi_register_gsi() acpi_unregister_gsi() to ACPI core code. Since the generic GSI<->domain mapping is based on IRQ domains, it can be extended as soon as a way to map an interrupt controller to an IRQ domain is implemented for ACPI in the IRQ domain layer. x86 and ia64 code for GSI mappings cannot rely on the generic GSI layer at present for legacy reasons, so they do not select the ACPI_GENERIC_GSI config options and keep relying on their arch specific GSI mapping layer. Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Acked-by: Hanjun Guo <hanjun.guo@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Don't unflatten device tree if acpi=force is passedHanjun Guo2015-03-263-2/+5
| | | | | | | | | | | | Since the policy is that once we pass acpi=force in the early param, we will not unflatten device tree even if ACPI is disabled in ACPI table init fails, so fix the code by comparinging both acpi_disabled and param_acpi_force before the device tree is unflattened. CC: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Enable ARM64 in KconfigGraeme Gregory2015-03-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add Kconfigs to build ACPI on ARM64, and make ACPI available on ARM64. acpi_idle driver is x86/IA64 dependent now, so make CONFIG_ACPI_PROCESSOR depend on X86 || IA64, and implement it on ARM64 in the future. CC: Rafael J. Wysocki <rjw@rjwysocki.net> CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> Signed-off-by: Al Stone <al.stone@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64Al Stone2015-03-262-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | ACPI reduced hardware mode is disabled by default, but ARM64 can only run properly in ACPI hardware reduced mode, so select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64. If the firmware is not using hardware reduced ACPI mode, we will disable ACPI to avoid nightmare such as accessing some registers which are not available on ARM64. CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Al Stone <al.stone@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* clocksource / arch_timer: Parse GTDT to initialize arch timerHanjun Guo2015-03-261-0/+7
| | | | | | | | | | | | | | | | | | | | Using the information presented by GTDT (Generic Timer Description Table) to initialize the arch timer (not memory-mapped). CC: Daniel Lezcano <daniel.lezcano@linaro.org> CC: Thomas Gleixner <tglx@linutronix.de> Originally-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* irqchip: Add GICv2 specific ACPI boot supportTomasz Nowicki2015-03-263-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACPI kernel uses MADT table for proper GIC initialization. It needs to parse GIC related subtables, collect CPU interface and distributor addresses and call driver initialization function (which is hardware abstraction agnostic). In a similar way, FDT initialize GICv1/2. NOTE: This commit allow to initialize GICv1/2 basic functionality. While now simple GICv2 init call is used, any further GIC features require generic infrastructure for proper ACPI irqchip initialization. That mechanism and stacked irqdomains to support GICv2 MSI/virtualization extension, GICv3/4 and its ITS are considered as next steps. CC: Jason Cooper <jason@lakedaemon.net> CC: Marc Zyngier <marc.zyngier@arm.com> CC: Thomas Gleixner <tglx@linutronix.de> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsiHanjun Guo2015-03-261-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce ACPI_IRQ_MODEL_GIC which is needed for ARM64 as GIC is used, and then register device's gsi with the core IRQ subsystem. acpi_register_gsi() is similar to DT based irq_of_parse_and_map(), since gsi is unique in the system, so use hwirq number directly for the mapping. We are going to implement stacked domains when GICv2m, GICv3, ITS support are added. CC: Marc Zyngier <marc.zyngier@arm.com> Originally-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ACPI / processor: Make it possible to get CPU hardware ID via GICCHanjun Guo2015-03-261-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained from the GICC Structure introduced by ACPI 5.1, since MPIDR for ARM64 is 64-bit, so typedef u64 for phys_cpuid_t. The ARM architecture defines the MPIDR register as the CPU hardware identifier. This patch adds the code infrastructure to retrieve the MPIDR values from the ARM ACPI GICC structure in order to look-up the kernel CPU hardware ids required by the ACPI core code to identify CPUs. CC: Rafael J. Wysocki <rjw@rjwysocki.net> CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ACPI / processor: Introduce phys_cpuid_t for CPU hardware IDCatalin Marinas2015-03-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | CPU hardware ID (phys_id) is defined as u32 in structure acpi_processor, but phys_id is used as int in acpi processor driver, so it will lead to some inconsistence for the drivers. Furthermore, to cater for ACPI arch ports that implement 64 bits CPU ids a generic CPU physical id type is required. So introduce typedef u32 phys_cpuid_t in a common file, and introduce a macro PHYS_CPUID_INVALID as (phys_cpuid_t)(-1) if it's not defined by other archs, this will solve the inconsistence in acpi processor driver, and will prepare for the ACPI on ARM64 for the 64 bit CPU hardware ID in the following patch. CC: Rafael J Wysocki <rjw@rjwysocki.net> Suggested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> [hj: reworked cpu physid map return codes] Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Parse MADT for SMP initializationHanjun Guo2015-03-257-8/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MADT contains the information for MPIDR which is essential for SMP initialization, parse the GIC cpu interface structures to get the MPIDR value and map it to cpu_logical_map(), and add enabled cpu with valid MPIDR into cpu_possible_map. ACPI 5.1 only has two explicit methods to boot up SMP, PSCI and Parking protocol, but the Parking protocol is only specified for ARMv7 now, so make PSCI as the only way for the SMP boot protocol before some updates for the ACPI spec or the Parking protocol spec. Parking protocol patches for SMP boot will be sent to upstream when the new version of Parking protocol is ready. CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> CC: Mark Rutland <mark.rutland@arm.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Olof Johansson <olof@lixom.net> Reviewed-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Get PSCI flags in FADT for PSCI initGraeme Gregory2015-03-254-28/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two flags: PSCI_COMPLIANT and PSCI_USE_HVC. When set, the former signals to the OS that the firmware is PSCI compliant. The latter selects the appropriate conduit for PSCI calls by toggling between Hypervisor Calls (HVC) and Secure Monitor Calls (SMC). FADT table contains such information in ACPI 5.1, FADT table was parsed in ACPI table init and copy to struct acpi_gbl_FADT, so use the flags in struct acpi_gbl_FADT for PSCI init. Since ACPI 5.1 doesn't support self defined PSCI function IDs, which means that only PSCI 0.2+ is supported in ACPI. CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: If we chose to boot from acpi then disable FDTGraeme Gregory2015-03-251-1/+2
| | | | | | | | | | | | | | | | | | | | | If the early boot methods of acpi are happy that we have valid ACPI tables and acpi=force has been passed, then do not unflat devicetree effectively disabling further hardware probing from DT. CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Introduce early_param "acpi=" to enable/disable ACPIAl Stone2015-03-252-5/+54
| | | | | | | | | | | | | | | | | | | | | | | | This implements the following policy to decide whether ACPI should be used to boot the system: - acpi=off: ACPI will not be used to boot the system, even if there is no alternative available (e.g., device tree is empty) - acpi=force: only ACPI will be used to boot the system; if that fails, there will be no fallback to alternative methods (such as device tree) - otherwise, ACPI will be used as a fallback if the device tree turns out to lack a platform description; the heuristic to decide this is whether /chosen is the only node present at depth 1 CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> CC: Rafael J. Wysocki <rjw@rjwysocki.net> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@linaro.org> Tested-by: Timur Tabi <timur@codeaurora.org> Signed-off-by: Al Stone <al.stone@linaro.org> Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Introduce PCI stub functions for ACPIHanjun Guo2015-03-252-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ACPI depends CONFIG_PCI on x86 and ia64, in ARM64 server world we will have PCIe in most cases, but some of them may not, make CONFIG_ACPI depend CONFIG_PCI on ARM64 will satisfy both. With that case, we need some arch dependent PCI functions to access the config space before the PCI root bridge is created, and pci_acpi_scan_root() to create the PCI root bus. So introduce some stub function here to make ACPI core compile and revisit them later when implemented on ARM64. CC: Liviu Dudau <Liviu.Dudau@arm.com> CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ACPI / sleep: Introduce CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORTGraeme Gregory2015-03-252-0/+2
| | | | | | | | | | | | | | | | | | | | ACPI 5.1 does not currently support S states for ARM64 hardware but ACPI code will call acpi_target_system_state() and acpi_sleep_init() for device power management, so introduce CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT and select it for x86 and ia64 only to make sleep functions available, and also introduce stub function to allow other drivers to function until S states are defined for ARM64. It will be no functional change for x86 and IA64. Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ACPI: fix acpi_os_ioremap for arm64Mark Salter2015-03-251-0/+13
| | | | | | | | | | | | | | | | | | | The acpi_os_ioremap() function may be used to map normal RAM or IO regions. The current implementation simply uses ioremap_cache(). This will work for some architectures, but arm64 ioremap_cache() cannot be used to map IO regions which don't support caching. So for arm64, use ioremap() for non-RAM regions. CC: Rafael J Wysocki <rjw@rjwysocki.net> CC: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Robert Richter <rrichter@cavium.com> Tested-by: Timur Tabi <timur@codeaurora.org> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64 / ACPI: Get RSDP and ACPI boot-time tablesAl Stone2015-03-255-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we want to get ACPI tables to parse and then use the information for system initialization, we should get the RSDP (Root System Description Pointer) first, it then locates Extended Root Description Table (XSDT) which contains all the 64-bit physical address that pointer to other boot-time tables. Introduce acpi.c and its related head file in this patch to provide fundamental needs of extern variables and functions for ACPI core, and then get boot-time tables as needed. - asm/acenv.h for arch specific ACPICA environments and implementation, It is needed unconditionally by ACPI core; - asm/acpi.h for arch specific variables and functions needed by ACPI driver core; - acpi.c for ARM64 related ACPI implementation for ACPI driver core; acpi_boot_table_init() is introduced to get RSDP and boot-time tables, it will be called in setup_arch() before paging_init(), so we should use eary_memremap() mechanism here to get the RSDP and all the table pointers. FADT Major.Minor version was introduced in ACPI 5.1, it is the same as ACPI version. In ACPI 5.1, some major gaps are fixed for ARM, such as updates in MADT table for GIC and SMP init, without those updates, we can not get the MPIDR for SMP init, and GICv2/3 related init information, so we can't boot arm64 ACPI properly with table versions predating 5.1. If firmware provides ACPI tables with ACPI version less than 5.1, OS has no way to retrieve the configuration data that is necessary to init SMP boot protocol and the GIC properly, so disable ACPI if we get an FADT table with version less that 5.1 when acpi_boot_table_init() called. CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Yijing Wang <wangyijing@huawei.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Timur Tabi <timur@codeaurora.org> Tested-by: Robert Richter <rrichter@cavium.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Al Stone <al.stone@linaro.org> Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM64: allow late use of early_ioremapMark Salter2015-03-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Commit 0e63ea48b4d8 (arm64/efi: add missing call to early_ioremap_reset()) added a missing call to early_ioremap_reset(). This triggers a BUG if code tries using early_ioremap() after the early_ioremap_reset(). This is a problem for some ACPI code which needs short-lived temporary mappings after paging_init() but before acpi_early_init() in start_kernel(). This patch adds definitions for the __late_set_fixmap() and __late_clear_fixmap() which avoids the BUG by allowing later use of early_ioremap(). CC: Leif Lindholm <leif.lindholm@linaro.org> CC: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Mark Langsdorf <mlangsdo@redhat.com> Tested-by: Jon Masters <jcm@redhat.com> Tested-by: Robert Richter <rrichter@cavium.com> Tested-by: Timur Tabi <timur@codeaurora.org> Acked-by: Robert Richter <rrichter@cavium.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2015-03-151-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clock framework fixes from Michael Turquette: "The clk fixes for 4.0-rc4 comprise three themes. First are the usual driver fixes for new regressions since v3.19. Second are fixes to the common clock divider type caused by recent changes to how we round clock rates. This affects many clock drivers that use this common code. Finally there are fixes for drivers that improperly compared struct clk pointers (drivers must not deref these pointers). While some of these drivers have done this for a long time, this did not cause a problem until we started generating unique struct clk pointers for every consumer. A new function, clk_is_match was introduced to get these drivers working again and they are fixed up to no longer deref the pointers themselves" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: ASoC: kirkwood: fix struct clk pointer comparing ASoC: fsl_spdif: fix struct clk pointer comparing ARM: imx: fix struct clk pointer comparing clk: introduce clk_is_match clk: don't export static symbol clk: divider: fix calculation of initial best divider when rounding to closest clk: divider: fix selection of divider when rounding to closest clk: divider: fix calculation of maximal parent rate for a given divider clk: divider: return real rate instead of divider value clk: qcom: fix platform_no_drv_owner.cocci warnings clk: qcom: fix platform_no_drv_owner.cocci warnings clk: qcom: Add PLL4 vote clock clk: qcom: lcc-msm8960: Fix PLL rate detection clk: qcom: Fix slimbus n and m val offsets clk: ti: Fix FAPLL parent enable bit handling
| * ARM: imx: fix struct clk pointer comparingShawn Guo2015-03-111-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 035a61c314eb ("clk: Make clk API return per-user struct clk instances"), clk API users can no longer check if two struct clk pointers are pointing to the same hardware clock, i.e. struct clk_hw, by simply comparing two pointers. That's because with the per-user clk change, a brand new struct clk is created whenever clients try to look up the clock by calling clk_get() or sister functions like clk_get_sys() and of_clk_get(). This changes the original behavior where the struct clk is only created for once when clock driver registers the clock to CCF in the first place. The net change here is before commit 035a61c314eb the struct clk pointer is unique for given hardware clock, while after the commit the pointers returned by clk lookup calls become different for the same hardware clock. That said, the struct clk pointer comparing in the code doesn't work any more. Call helper function clk_is_match() instead to fix the problem. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge tag 'fixes-for-linus' of ↵Linus Torvalds2015-03-1563-221/+826
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Arnd Bergmann: "This is a rather unpleasantly large set of bug fixes for arm-soc, Most of them because of cross-tree dependencies for Exynos where we should have figured out the right path to merge things before the merge window, and then the maintainer being unable to sort things out in time during a business trip. The other changes contained here are the usual collection: MAINTAINERS file updates - Gregory Clement is now a co-maintainer for the legacy Marvell EBU platforms - A MAINTAINERS entry for the Freescale Vybrid platform that was added last year - Matt Porter no longer works as a maintainer on Broadcom SoCs Build-time issues - A compile-time error for at91 - Several minor DT fixes on at91, imx, exynos, socfpga, and omap - The new digicolor platform was not correctly enabled at all Configuration issues - Two defconfig fix for regressions using USB on versatile express and on OMAP3 - Enabling all 8 CPUs on Allwinner/SUNxi - Enabling the new STiH410 platform to be usable Bug fixes in platform code - A missing barrier for socfpga - Fixing LPDDR1 self-refresh mode on at91 - Fixing RTC interrupt numbers on Exynos3250 - Fixing a cache-coherency issues in CPU power-down on Exynos5 - Multiple small OMAP power management fixes" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (69 commits) MAINTAINERS: Add myself as co-maintainer to the legacy support of the mvebu SoCs ARM: at91: pm_slowclock: fix the compilation error ARM: at91/dt: fix USB high-speed clock to select UTMI ARM: at91/dt: fix at91 udc compatible strings ARM: at91/dt: declare matrix node as a syscon device ARM: vexpress: update CONFIG_USB_ISP1760 option ARM: digicolor: add the machine directory to Makefile ARM: STi: Add STiH410 SoC support MAINTAINERS: add Freescale Vybrid SoC MAINTAINERS: Remove self as ARM mach-bcm co-maintainer ARM: imx6sl-evk: set swbst_reg as vbus's parent reg ARM: imx6qdl-sabresd: set swbst_reg as vbus's parent reg ARM: at91/dt: at91sam9261: fix clocks and clock-names in udc definition ARM: OMAP2+: Fix wl12xx on dm3730-evm with mainline u-boot ARM: OMAP: enable TWL4030_USB in omap2plus_defconfig ARM: dts: dra7x-evm: avoid possible contention while muxing on CAN lines ARM: dts: dra7x-evm: Don't use dcan1_rx.gpio1_15 in DCAN pinctrl ARM: dts: am43xx: fix SLEWCTRL_FAST pinctrl binding ARM: dts: am33xx: fix SLEWCTRL_FAST pinctrl binding ARM: dts: OMAP5: fix polling intervals for thermal zones ...
| * \ Merge tag 'at91-fixes3' of ↵Arnd Bergmann2015-03-118-11/+14
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into fixes Pull "Third fixes batch for AT91 on 4.0" from Nicolas Ferre: - clock fixes for USB - compatible string changes for handling USB IP differences (+ needed AHB matrix syscon) - fix of a compilation error in PM code * tag 'at91-fixes3' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91: pm_slowclock: fix the compilation error ARM: at91/dt: fix USB high-speed clock to select UTMI ARM: at91/dt: fix at91 udc compatible strings ARM: at91/dt: declare matrix node as a syscon device ARM: at91/dt: at91sam9261: fix clocks and clock-names in udc definition
| | * | ARM: at91: pm_slowclock: fix the compilation errorWenyou Yang2015-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiling the kernel in thumb2 (CONFIG_THUMB2_KERNEL option activated), we hit a compilation crash. The error message is listed below: ---8< ----- Error: cannot use register index with PC-relative addressing -- `str r0,.saved_lpr' --->8---- Add the .arm directive in the assembly files related to power management. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | ARM: at91/dt: fix USB high-speed clock to select UTMINicolas Ferre2015-03-114-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UTMI clock must be selected by any high-speed USB IP. The logic behind it needs this particular clock. So, correct the clock in the device tree files affected. Reported-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: <stable@vger.kernel.org> #3.18
| | * | ARM: at91/dt: fix at91 udc compatible stringsBoris Brezillon2015-03-113-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The at91rm9200, at91sam9260, at91sam9261 and at91sam9263 SoCs have slightly different UDC IPs. Those differences were previously handled with cpu_is_at91xx macro which are about to be dropped for multi-platform support, thus we need to change compatible strings. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | ARM: at91/dt: declare matrix node as a syscon deviceBoris Brezillon2015-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no specific driver handling the AHB matrix, this is a simple syscon device. the matrix is needed by several other drivers including the USB on some SoCs (at91sam9261 for instance). Without this definition, the USB will not work on these SoCs. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | ARM: at91/dt: at91sam9261: fix clocks and clock-names in udc definitionBoris Brezillon2015-03-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Peripheral clock is named pclk and system clock is named hclk (those are the names expected by the at91_udc driver). Drop the deprecated usb_clk (formerly used to configure the usb clock rate which is now directly configurable through hclk). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | | Merge tag 'imx-fixes-4.0' of ↵Arnd Bergmann2015-03-112-0/+4
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes Pull "The i.MX fixes for 4.0" from Shawn Guo: It includes a couple of i.MX6 dts fixes, which set an input supply to vbus regulator. Without the fixes, the voltage of vbus is incorrect after system boots up. * tag 'imx-fixes-4.0' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx6sl-evk: set swbst_reg as vbus's parent reg ARM: imx6qdl-sabresd: set swbst_reg as vbus's parent reg
| | * | | ARM: imx6sl-evk: set swbst_reg as vbus's parent regPeter Chen2015-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB vbus 5V is from PMIC SWBST, so set swbst_reg as vbus's parent reg, it fixed a bug that the voltage of vbus is incorrect due to swbst_reg is disabled after boots up. Cc: stable@vger.kernel.org Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | ARM: imx6qdl-sabresd: set swbst_reg as vbus's parent regPeter Chen2015-03-111-0/+2
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB vbus 5V is from PMIC SWBST, so set swbst_reg as vbus's parent reg, it fixed a bug that the voltage of vbus is incorrect due to swbst_reg is disabled after boots up. Cc: stable@vger.kernel.org Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: vexpress: update CONFIG_USB_ISP1760 optionSudeep Holla2015-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7ef077a8ad35 ("usb: isp1760: Move driver from drivers/usb/host/ to drivers/usb/isp1760/") moved the isp1760 driver and changed the Kconfig option. This makes CONFIG_USB_ISP1760_HCD not selectable directly anymore. This results in driver being not compiled in when using vexpress_defconfig and the USB is non-functional. This patch updates the CONFIG_USB_ISP1760_HCD to CONFIG_USB_ISP1760 to get back USB functional on vexpress platforms. Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reported-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | ARM: digicolor: add the machine directory to MakefileBaruch Siach2015-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the digicolor specific DT_MACHINE_START entry visible. Fixes: df8d742e929 (ARM: initial support for Conexant Digicolor CX92755 SoC) Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | Merge tag 'fixes-v4.0-rc2' of ↵Arnd Bergmann2015-03-1118-130/+187
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Pull "omap fixes against v4.0-rc2" from Tony Lindgren: Fixes for various omap variants, mostly minor fixes for various SoCs with the bigger changes being for the dra7 clocks and hwmod data: - Fix wl12xx for dm3730-evm - Fix omap4 prm save and clea - Fix hwmod clkdm use count - Fix hwmod data for pcie on dra7 - Fix lockdep for hwmod - Fix USB on most omap3 boars by enabling it in the defconfig - Fix the bypass clock source for omap5 and dra7 - Fix the ehrpwm clock for am33xx and am43xx - Enable AES and SHAM for BeagleBone white - Use rmii clock for am335x-lxm - Fix polling intervals for omap5 thermal zones - Fix slewctrl for am33xx and am43xx - Fix dra7-evm dcan pinctrl * tag 'fixes-v4.0-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Fix wl12xx on dm3730-evm with mainline u-boot ARM: OMAP: enable TWL4030_USB in omap2plus_defconfig ARM: dts: dra7x-evm: avoid possible contention while muxing on CAN lines ARM: dts: dra7x-evm: Don't use dcan1_rx.gpio1_15 in DCAN pinctrl ARM: dts: am43xx: fix SLEWCTRL_FAST pinctrl binding ARM: dts: am33xx: fix SLEWCTRL_FAST pinctrl binding ARM: dts: OMAP5: fix polling intervals for thermal zones ARM: dts: am335x-lxm: Use rmii-clock-ext ARM: dts: am335x-bone-common: enable aes and sham ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx ARM: dts: am33xx-clocks: Fix ehrpwm tbclk data on am33xx ARM: dts: OMAP5: Fix the bypass clock source for dpll_iva and others ARM: dts: DRA7x: Fix the bypass clock source for dpll_iva and others ARM: OMAP4+: PRM: fix omap4 version of prm_save_and_clear_irqen ARM: OMAP2+: hwmod: fix deassert hardreset clkdm usecounting ARM: DRA7: hwmod_data: Fix hwmod data for pcie ARM: omap2+: omap_hwmod: Set unique lock_class_key per hwmod
| | * | | ARM: OMAP2+: Fix wl12xx on dm3730-evm with mainline u-bootTony Lindgren2015-03-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I upgraded my u-boot and noticed that wl12xx stopped working. Turns out the kernel is not setting the quirk for the MMC2 copy clock while the eariler bootloader I had was setting it. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | Merge tag 'for-v4.0-rc/omap-fixes-a' of ↵Tony Lindgren2015-03-064-86/+32
| | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.0/fixes ARM: OMAP2+: first set of hwmod and PRCM fixes for v4.0-rc This series fixes the following bugs: - a lockdep problem with the OMAP hwmod code; - incorrect PCIe hwmod data for the DRA7xx chips; - the clockdomain handling in the hardreset deassertion code, preventing idle; - the use of an IRQ status register rather than an IRQ enable register in the OMAP4 PRM code. Basic build, boot, and PM test results are available here: http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.0-rc/20150301165949/
| | | * | | ARM: OMAP4+: PRM: fix omap4 version of prm_save_and_clear_irqenTero Kristo2015-03-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was incorrectly reading the irq status registers during the save and clear, instead of the irq enable. This worked because there is only one user for the prcm interrupts currently, namely the io-chain. Whenever the function was called, an io-chain interrupt was both pending and enabled. Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: OMAP2+: hwmod: fix deassert hardreset clkdm usecountingTero Kristo2015-03-011-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deasserting hardreset increases the usecount for the hwmod parent clockdomain always, however usecount is only decreased at end in certain error cases. This causes software supervised clockdomains to remain always on, preventing idle. Fixed by always releasing the hwmods clockdomain parent when exiting the function. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Carlos Hernandez <ceh@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: DRA7: hwmod_data: Fix hwmod data for pcieKishon Vijay Abraham I2015-02-261-79/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed hwmod data for pcie by having the correct module mode offset. Previously this module mode offset was part of pcie PHY which was wrong. Now this module mode offset was moved to pcie hwmod and removed the hwmod data for pcie phy. While at that renamed pcie_hwmod to pciess_hwmod in order to match with the name given in TRM. This helps to get rid of the following warning "omap_hwmod: pcie1: _wait_target_disable failed" [Grygorii.Strashko@linaro.org: Found the issue that actually caused "omap_hwmod: pcie1: _wait_target_disable failed"] Signed-off-by: Grygorii Strashko <Grygorii.Strashko@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: omap2+: omap_hwmod: Set unique lock_class_key per hwmodPeter Ujfalusi2015-02-262-0/+2
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add struct lock_class_key to omap_hwmod struct and use it to set unique lockdep class per hwmod. This will ensure that lockdep will know that each omap_hwmod->_lock should be treated as separate class and will not give false warning about deadlock or other issues due to nested use of hwmods. DRA7x's ATL hwmod is one example for this since McASP can select ATL clock as functional clock, which will trigger nested oh->_lock usage. This will trigger false warning from lockdep validator as it is dealing with classes and for it all hwmod clocks are the same class. Suggested-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | ARM: OMAP: enable TWL4030_USB in omap2plus_defconfigAaro Koskinen2015-03-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable TWL4030_USB which is used at least on Nokia N900/N950/N9 (OMAP3) and BeagleBoard. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> [tony@atomide.com: updated comments] Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: dts: dra7x-evm: avoid possible contention while muxing on CAN linesRoger Quadros2015-03-062-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCAN1 RX and TX lines are internally pulled high according to [1]. While muxing between DCAN mode and SAFE mode we make sure that the same pull direction is set to minimize opposite pull contention during the switching window. [1] in DRA7 data manual, Ball characteristics table 4-2, DSIS colum shows the state driven to the peripheral input while in the deselcted mode. DSIS - De-Selected Input State. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: dts: dra7x-evm: Don't use dcan1_rx.gpio1_15 in DCAN pinctrlRoger Quadros2015-03-062-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rev.F onwards ball G19 (dcan1_rx) is used as a GPIO for some other function so don't include it in DCAN pinctrl node. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: dts: OMAP5: fix polling intervals for thermal zonesTero Kristo2015-03-063-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP4 has a finer counter granularity, which allows for a delay of 1000ms in the thermal zone polling intervals. OMAP5 has a different counter mechanism, which allows at maximum a 500ms timer. Adjust the cpu thermal zone polling interval accordingly. Without this patch, the polling interval information is simply ignored, and the following thermal warnings are printed during boot (assuming thermal is enabled); [ 1.545343] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported [ 1.552691] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported [ 1.560029] ti-soc-thermal 4a0021e0.bandgap: Delay 1000 ms is not supported Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: dts: am335x-lxm: Use rmii-clock-extGeorge McCollister2015-03-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use external clock for RMII since the internal clock doesn't meet the jitter requirements. Signed-off-by: George McCollister <george.mccollister@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: dts: am335x-bone-common: enable aes and shamMatt Porter2015-03-062-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beaglebone Black doesn't have AES and SHAM enabled like the original Beaglebone White dts. This breaks applications that leverage the crypto blocks so fix this by enabling these nodes in the am335x-bone-common.dtsi. With this change, enabling the nodes in am335x-bone.dts is no longer required so remove them. Signed-off-by: Matt Porter <mporter@konsulko.com> Acked-by: Robert Nelson <robertcnelson@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-31 00:23:52 +0000