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* ARM: OMAP4+: Move SRAM data to DTRajendra Nayak2014-09-187-29/+19
| | | | | | | | | | | | | | | | Use drivers/misc/sram.c driver to manage SRAM on all DT only OMAP platforms (am33xx, am43xx, omap4 and omap5) instead of the existing private plat-omap/sram.c Address and size related data is removed from mach-omap2/sram.c and now passed to drivers/misc/sram.c from DT. Users can hence use general purpose allocator apis instead of OMAP private ones to manage and use SRAM. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: AM335x: Get rid of unused sram init functionRajendra Nayak2014-09-181-7/+0
| | | | | | | | Remove the empty am33xx_sram_init() function. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: omap2plus_defconfig: Enable some display featuresTony Lindgren2014-09-181-1/+21
| | | | | | | | | | | | | Now that we have panel support for DT based booting, let's make it usable and enable most things as modules. Note that omap3 boards need also the ads7847 module for the panel that we're now changing to a loadable module. And n900 seems to require setting the brightness via sysfs for acx565akm/brightness after modprobe of panel_sony_acx565akm and omapfb. Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: omap2plus_defconfig: Enable battery and reset driversTony Lindgren2014-09-181-0/+7
| | | | | | | Since many omaps run on battery, we should have the battery drivers enabled. Let's also enable the reset driver. Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: omap2plus_defconfig: Add support for distros with systemdTony Lindgren2014-09-181-2/+22
| | | | | | | | | | Some distros are now using systemd, so let's enable most of what's recommended at: http://cgit.freedesktop.org/systemd/systemd/tree/README Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: omap2plus_defconfig: Add cpufreq to defconfigTony Lindgren2014-09-181-0/+10
| | | | | | | | | | | | | | | | | Note that we can now use the CONFIG_GENERIC_CPUFREQ_CPU0, so let's only enable that. Let's use CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND as suggested by Nishant. And also let's enable thermal as explained by Nishant Menon: Many TI SoCs using Highest frequency is not really too nice of an idea for long periods of time. And not everything is upstream to support things optimially - example avs class 0, 1.5 ABB consolidation with cpufreq etc.. We definitely need thermal enabled as well for device safety needs. [tony@atomide.com: updated per Nishant's suggestions] Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: omap2plus_defconfig: Shrink with savedefconfigTony Lindgren2014-09-181-16/+3
| | | | | | | This saves few lines and makes it easier to make patches against omap2plus_defconfig. Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP3: Use manual idle for UARTs because of DMA errataTony Lindgren2014-09-181-4/+4
| | | | | | | | | | | | | | In sprz318f.pdf "Usage Note 2.7" says that UARTs cannot acknowledge idle requests in smartidle mode when configured for DMA operations. This prevents L4 from going idle. So let's use manual idle mode instead. Otherwise systems using Sebastian's 8250 patches with DMA will never enter deeper idle states because of the errata above. Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2+: Add hwmod flag for HWMOD_RECONFIG_IO_CHAINTony Lindgren2014-09-183-4/+8
| | | | | | | | | | | | | | Commit cc824534d4fe ("ARM: OMAP2+: hwmod: Rearm wake-up interrupts for DT when MUSB is idled") fixed issues with hung UART wake-up events by calling _reconfigure_io_chain() when MUSB is connected or disconnected. As pointed out by Paul Walmsley, we may need to also call _reconfigure_io_chain() in other cases, so it should be a separate flag. Let's add HWMOD_RECONFIG_IO_CHAIN as suggested by Paul. Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7Nishanth Menon2014-09-091-4/+8
| | | | | | | | | | | | | | | | OMAP4, OMAP5 and DRA7 share a lot of common logic and data structures. These have been enabled in the previous patches, however, this also means that OMAP5 or DRA7 only builds also need to build OMAP4 logic. Update to reuse OMAP4 logic. This fixes the 'undefined reference to 'omap4_pm_init_early'' in OMAP5 or DRA7 only builds. Fixes: 6af16a1dac5465c ("ARM: DRA7: Add hook in SoC initcalls to enable pm initialization") Fixes: 628ed4717000789 ("ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization") Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: dts: OMAP3+: Add PRM interruptNishanth Menon2014-09-084-0/+4
| | | | | | | | | Provide OMAP3, 4 and OMAP5 with interrupt number for PRM And for DRA7, provide crossbar number for prm interrupt. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: omap: Remove stray ARCH_HAS_OPP referencesMark Brown2014-09-081-5/+0
| | | | | | | | | | OPP is now a normal kernel library selected by its users rather than a feature that architectures need to enable so ARCH_HAS_OPP serves no function any more - remove the selects. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: DRA7: Add hook in SoC initcalls to enable pm initializationRajendra Nayak2014-09-082-1/+4
| | | | | | | | | | | | With consolidated code, now we can add the required hooks for DRA7 to enable power management. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: minor modifications] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'pull/v3.18/for-omap-soc' of ↵Tony Lindgren2014-09-0813-64/+275
|\ | | | | | | https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/soc
| * ARM: OMAP5: Add hook in SoC initcalls to enable pm initializationSantosh Shilimkar2014-09-082-1/+4
| | | | | | | | | | | | | | | | | | | | | | With consolidated code, now we can add the required hooks for OMAP5 to enable power management. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor rebase updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: Enable CPU RET on suspendRajendra Nayak2014-09-084-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR and instead attempt a CPU RET and side effect, MPU RET in suspend. NOTE: the hardware was originally designed to be capable of achieving deep power states such as OFF and OSWR, however due to various issues and risks, deepest valid state was determined to be CSWR - hence we use the errata framework to handle this case. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplugSantosh Shilimkar2014-09-081-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug logic. On OMAP5, DRA7, we do not need this in place yet, also, currently the CPU startup pointer is located in omap4_cpu_pm_info instead of cpu_pm_ops. So, isolate the function to hotplug_restart pointer in cpu_pm_ops where it should have belonged, initalize them as per valid startup pointers for OMAP4430/60 as in current logic, however provide dummy_cpu_resume to be the startup location as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: split this out of original code and isolate it] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Avoid all SAR savesRajendra Nayak2014-09-081-21/+34
| | | | | | | | | | | | | | | | | | | | | | | | Get rid of all assumptions about always having a sar base on *all* OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at this point for OMAP5 either. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: Split and optimize] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomainsSantosh Shilimkar2014-09-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the standard power-management technique, the OMAP5 / DRA7 MPU subsystem also employs an SR3-APG (mercury) power management technology to reduce leakage. It allows for full logic and memories retention on MPU_C0 and MPU_C1 and is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the OMAP5 and DRA7 family of processors. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor consolidation] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by defaultSantosh Shilimkar2014-09-083-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables MPUSS ES2 power management mode using ES2_PM_MODE in AMBA_IF_MODE register. 0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together. Broken! Fortunately, we do not support this anymore. 0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode independently. This is one time settings thanks to always ON domain. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor conflict resolutions, consolidation for DRA7] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependencySantosh Shilimkar2014-09-081-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With EMIF clock-domain put under hardware supervised control, memory corruption and untraceable crashes are observed on OMAP5. Further investigation revealed that there is a weakness in the PRCM on this specific dynamic depedency. The recommendation is to set MPUSS static dependency towards EMIF clock-domain to avoid issues. This recommendation holds good for DRA7 family of devices as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [rnayak@ti.com: DRA7] Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: conflict resolution, dra7] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Update CPU context register offsetSantosh Shilimkar2014-09-081-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same context offset as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [rnayak@ti.com: for DRA7] Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: rebase, split/merge etc..] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: AM437x: use pdata quirks for pinctrl informationKeerthy2014-09-081-0/+3
| | | | | | | | | | | | Provide pdata-quirks for Am437x processor family. Signed-off-by: Keerthy <j-keerthy@ti.com>
| * ARM: DRA7: use pdata quirks for pinctrl informationNishanth Menon2014-09-081-0/+3
| | | | | | | | | | | | Provide pdata-quirks for DRA7 processor family. Signed-off-by: Nishanth Menon <nm@ti.com>
| * ARM: OMAP5: use pdata quirks for pinctrl informationNishanth Menon2014-09-081-0/+4
| | | | | | | | | | | | Provide pdata-quirks for OMAP5 processor family. Signed-off-by: Nishanth Menon <nm@ti.com>
| * ARM: OMAP3+: PRM: register interrupt information from DTNishanth Menon2014-09-081-0/+18
| | | | | | | | | | | | | | | | | | | | Allow the PRM interrupt information to be picked up from device tree. OMAP3 may use legacy boot and needs to be compatible with old dtbs (without interrupt populated), for these, we use the value which is pre-populated. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4+: PRM: Enable wakeup capability for OMAP5, DRA7Nishanth Menon2014-09-081-1/+1
| | | | | | | | | | | | | | | | OMAP5 and DRA7 can now use pinctrl based I/O daisychain wakeup capability. So, enable the support. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4+: PRM: remove "wkup" eventNishanth Menon2014-09-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | "wkup" event at bit offset 0 exists only on OMAP3. OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3. The same applies to AM437x as well. Remove the wrong definition. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4+: PRM: register interrupt information from DTNishanth Menon2014-09-081-0/+40
| | | | | | | | | | | | | | | | | | Allow the PRM interrupt information to be picked up from device tree. the only exception is for OMAP4 which uses values pre-populated and allows compatibility with older dtb. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4: PRM: use the generic prm_inst to allow logic to be abstractedNishanth Menon2014-09-081-9/+38
| | | | | | | | | | | | | | | | use the generic function to pick up the prm_instance for a generic logic which can be reused from OMAP4+ Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4+: prminst: provide function to find prm_dev instance offsetNishanth Menon2014-09-082-15/+28
| | | | | | | | | | | | | | | | | | | | PRM device instance can vary depending on SoC. We already handle the same during reset of the device, However, this is also needed for other logic instances. So, first abstract this out to a generic function. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | Merge branch 'pull/v3.18/powerdomain-fixes' of ↵Tony Lindgren2014-09-086-16/+106
|\ \ | | | | | | | | | https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/fixes-not-urgent
| * | ARM: OMAP4+: PM: Use only valid low power state for CPU hotplugNishanth Menon2014-09-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Not all SoCs support OFF mode - for example DRA74/72. So, use valid power state during CPU hotplug. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP4+: PM: use only valid low power state for suspendNishanth Menon2014-09-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are using power domain state as RET and logic state as OFF. This state is OSWR. This may not always be supported on ALL power domains. In fact, on certain power domains, this might result in a hang on certain platforms. Instead, depend on powerdomain data to provide accurate information about the supported powerdomain states and use the appropriate function to query and use it as part of suspend path. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP4+: PM: Make logic state programmableNishanth Menon2014-09-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the logic state as different for each power domain. This allows us to customize the deepest power state we should target over all for each powerdomain in the follow on patches. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP2+: powerdomain: introduce logic for finding valid power domainNishanth Menon2014-09-082-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | powerdomain configuration in OMAP is done using PWRSTCTRL register for each power domain. However, PRCM lets us write any value we'd like to the logic and power domain target states, however the SoC integration tends to actually function only at a few discrete states. These valid states are already in our powerdomains_xxx_data.c file. So, provide a function to easily query valid low power state that the power domain is allowed to go to. Based on work originally done by Jean Pihet <j-pihet@ti.com> https://patchwork.kernel.org/patch/1325091/ . There is no attempt to create a new powerdomain solution here, except fixing issues seen attempting invalid programming attempts. Future consolidation to the generic powerdomain framework should consider this requirement as well. Similar solutions have been done in product kernels in the past such as: https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdmsNishanth Menon2014-09-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | No need to invoke callback when the clkdm pointer is NULL. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP5: powerdomain data: fix powerdomain powerstateNishanth Menon2014-09-081-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update the power domain power states for final production chip capability. OFF mode, OSWR etc have been descoped for various domains. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstateNishanth Menon2014-09-082-7/+8
| |/ | | | | | | | | | | | | | | | | DRA7 supports only CSWR for CPU, MPU power domains. Core power domain supports upto INA. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | ARM: dts: am335x-bone*: Fix model name and update compatibility informationNishanth Menon2014-09-033-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beaglebone white and beaglebone black differ in tiny little aspects. This is the reason why we maintain seperate dts for these platforms. However, there is no real way to decode from dtb which platform it is since compatible and model name are the same for both platforms. Fix this so that beaglebone black and beaglebone are identifiable, while maintaining compatibility for older zImages which might use old beaglebone compatible flag for black as well. Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: dts: omap4-panda: Fix model and SoC family detailsNishanth Menon2014-09-033-3/+10
| | | | | | | | | | | | | | | | | | | | | | Currently we claim that omap4-panda and omap4-panda-es are essentially the same, but they are not since PandaBoard-ES uses OMAP4460 and PandaBoard uses OMAP4430. So, split the common definition and make the model name available. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge tag 'xtensa-20140830' of git://github.com/czankel/xtensa-linuxLinus Torvalds2014-08-3124-217/+497
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull Xtensa updates from Chris Zankel: "Xtensa improvements for 3.17: - support highmem on cores with aliasing data cache. Enable highmem on kc705 by default - simplify addition of new core variants (no need to modify Kconfig / Makefiles) - improve robustness of unaligned access handler and its interaction with window overflow/underflow exception handlers - deprecate atomic and spill registers syscalls - clean up Kconfig: remove orphan MATH_EMULATION, sort 'select' statements - wire up renameat2 syscall. Various fixes: - fix address checks in dma_{alloc,free}_coherent (runtime BUG) - fix access to THREAD_RA/THREAD_SP/THREAD_DS (debug build breakage) - fix TLBTEMP_BASE_2 region handling in fast_second_level_miss (runtime unrecoverable exception) - fix a6 and a7 handling in fast_syscall_xtensa (runtime userspace register clobbering) - fix kernel/user jump out of fast_unaligned (potential runtime unrecoverabl exception) - replace termios IOCTL code definitions with constants (userspace build breakage)" * tag 'xtensa-20140830' of git://github.com/czankel/xtensa-linux: (25 commits) xtensa: deprecate fast_xtensa and fast_spill_registers syscalls xtensa: don't allow overflow/underflow on unaligned stack xtensa: fix a6 and a7 handling in fast_syscall_xtensa xtensa: allow single-stepping through unaligned load/store xtensa: move invalid unaligned instruction handler closer to its users xtensa: make fast_unaligned store restartable xtensa: add double exception fixup handler for fast_unaligned xtensa: fix kernel/user jump out of fast_unaligned xtensa: configure kc705 for highmem xtensa: support highmem in aliasing cache flushing code xtensa: support aliasing cache in kmap xtensa: support aliasing cache in k[un]map_atomic xtensa: implement clear_user_highpage and copy_user_highpage xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss xtensa: allow fixmap and kmap span more than one page table xtensa: make fixmap region addressing grow with index xtensa: fix access to THREAD_RA/THREAD_SP/THREAD_DS xtensa: add renameat2 syscall xtensa: fix address checks in dma_{alloc,free}_coherent xtensa: replace IOCTL code definitions with constants ...
| * \ Merge tag 'xtensa-for-next-20140815' into for_nextChris Zankel2014-08-1824-217/+497
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xtensa improvements for 3.17: - support highmem on cores with aliasing data cache. Enable highmem on kc705 by default; - simplify addition of new core variants (no need to modify Kconfig / Makefiles); - improve robustness of unaligned access handler and its interaction with window overflow/underflow exception handlers; - deprecate atomic and spill registers syscalls; - clean up Kconfig: remove orphan MATH_EMULATION, sort 'select' statements; - wire up renameat2 syscall. Various fixes: - fix address checks in dma_{alloc,free}_coherent (runtime BUG); - fix access to THREAD_RA/THREAD_SP/THREAD_DS (debug build breakage); - fix TLBTEMP_BASE_2 region handling in fast_second_level_miss (runtime unrecoverable exception); - fix a6 and a7 handling in fast_syscall_xtensa (runtime userspace register clobbering); - fix kernel/user jump out of fast_unaligned (potential runtime unrecoverable exception); - replace termios IOCTL code definitions with constants (userspace build breakage). Signed-off-by: Chris Zankel <chris@zankel.net>
| | * xtensa: deprecate fast_xtensa and fast_spill_registers syscallsMax Filippov2014-08-142-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These syscalls are not used by userspace tools for some time now, and they have issues when called with invalid arguments. It's not worth changing signal delivery mechanism as we don't expect any new users for these syscalls. Let's keep them for backwards compatibility under #ifdef, disabled by default. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: don't allow overflow/underflow on unaligned stackMax Filippov2014-08-143-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Double exceptions that happen during register window overflow/underflow are handled in the topmost stack frame, as if it was the only exception that occured. However unaligned access exception handler is special because it needs to analyze instruction that caused the exception, but the userspace instruction that triggered window exception is completely irrelevant. Unaligned data access is rather normal in the generic userspace code, but stack pointer manipulation must always be done by architecture-aware code and thus unaligned stack means a serious problem anyway. Use the default unaligned access handler that raises SIGBUS in case of unaligned access in window overflow/underflow handler. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: fix a6 and a7 handling in fast_syscall_xtensaMax Filippov2014-08-141-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove restoring a6 on some return paths and instead modify and restore it in a single place, using symbolic name. Correctly restore a7 from PT_AREG7 in case of illegal a6 value. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: allow single-stepping through unaligned load/storeMax Filippov2014-08-141-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Update icount when icountlevel is non-zero but not greater than EXCM level when load/store instruction is successfully emulated. This allows single-stepping over such instruction in userspace debugger. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: move invalid unaligned instruction handler closer to its usersMax Filippov2014-08-141-33/+29
| | | | | | | | | | | | | | | | | | | | | | | | With this change a threaded jump from .Linvalid_instruction_load to .Linvalid_instruction can be removed and more code may be added to common load/store exit path. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: make fast_unaligned store restartableMax Filippov2014-08-141-32/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fast_unaligned may encounter DTLB miss or SEGFAULT during the store emulation. Don't update epc1 and lcount until after the store emulation is complete, so that the faulting store instruction could be replayed. Remove duplicate code handling zero overhead loops and calculate new epc1 and lcount in one place. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| | * xtensa: add double exception fixup handler for fast_unalignedMax Filippov2014-08-141-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | fast_unaligned_fixup restores user registers and runs normal exception handler in the current stack frame. Unaligned load/store is retried after that. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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