summaryrefslogtreecommitdiffstats
path: root/drivers/char/agp/intel-gtt.c
Commit message (Collapse)AuthorAgeFilesLines
...
| * agp/intel: map more registers for use by the GTT codeJesse Barnes2012-03-291-1/+5
| | | | | | | | | | | | | | | | | | | | | | We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the register for doing so is above the range we normally map. Map the whole register space to make sure we can get it. v2: only map the larger space on gen7+ (Daniel) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: disable ppgtt on snb when dmar is enabledDaniel Vetter2012-04-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Totally unexpected that this regressed. Luckily it sounds like we just need to have dmar disable on the igfx, not the entire system. At least that's what a few days of testing between Tony Vroon and me indicates. Reported-by: Tony Vroon <tony@linx.net> Cc: Tony Vroon <tony@linx.net> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43024 Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: add Ivy Bridge GT2 Server entriesEugeni Dodonov2012-04-021-0/+2
|/ | | | | | | | This adds PCI ID for IVB GT2 server variant which we were missing. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> [danvet: fix up conflict because the patch has been diffed against next. tsk.] Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* agp/intel-gtt: export the gtt pagetable iomappingDaniel Vetter2012-02-091-0/+1
| | | | | | | | | | | We need this because ppgtt page directory entries need to be in the global gtt pagetable. Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* agp/intel-gtt: export the scratch page dma addressDaniel Vetter2012-02-091-5/+4
| | | | | | | | | | | To implement a PPGTT for drm/i915 that fully aliases the GTT, we also need to properly alias the scratch page. Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* agp: iommu_gfx_mapped only available if CONFIG_INTEL_IOMMU is setKeith Packard2011-11-081-2/+3
| | | | | | | | | | | Kernels with no iommu support cannot ever need the Ironlake work-around, so never enable it in that case. Might be better to completely remove the work-around from the kernel in this case? Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* drm/i915: fix if statement (bogus semi-colon)Dan Carpenter2011-11-081-1/+1
| | | | | | | | The semi-colon is a typo here and it makes the if statement unconditional. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* Merge branch 'drm-core-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2011-10-281-0/+28
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'drm-core-next' of git://people.freedesktop.org/~airlied/linux: (290 commits) Revert "drm/ttm: add a way to bo_wait for either the last read or last write" Revert "drm/radeon/kms: add a new gem_wait ioctl with read/write flags" vmwgfx: Don't pass unused arguments to do_dirty functions vmwgfx: Emulate depth 32 framebuffers drm/radeon: Lower the severity of the radeon lockup messages. drm/i915/dp: Fix eDP on PCH DP on CPT/PPT drm/i915/dp: Introduce is_cpu_edp() drm/i915: use correct SPD type value drm/i915: fix ILK+ infoframe support drm/i915: add DP test request handling drm/i915: read full receiver capability field during DP hot plug drm/i915/dp: Remove eDP special cases from bandwidth checks drm/i915/dp: Fix the math in intel_dp_link_required drm/i915/panel: Always record the backlight level again (but cleverly) i915: Move i915_read/write out of line drm/i915: remove transcoder PLL mashing from mode_set per specs drm/i915: if transcoder disable fails, say which drm/i915: set watermarks for third pipe on IVB drm/i915: export a CPT mode set verification function drm/i915: fix transcoder PLL select masking ...
| * drm/i915: ILK + VT-d workaroundBen Widawsky2011-10-201-0/+28
| | | | | | | | | | | | | | | | | | | | | | Idle the GPU before doing any unmaps. We know if VT-d is in use through an exported variable from iommu code. This should avoid a known HW issue. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Keith Packard <keithp@keithp.com>
* | iommu: Rename the DMAR and INTR_REMAP config optionsSuresh Siddha2011-09-211-2/+2
|/ | | | | | | | | | | | | | | | | | | | Change the CONFIG_DMAR to CONFIG_INTEL_IOMMU to be consistent with the other IOMMU options. Rename the CONFIG_INTR_REMAP to CONFIG_IRQ_REMAP to match the irq subsystem name. And define the CONFIG_DMAR_TABLE for the common ACPI DMAR routines shared by both CONFIG_INTEL_IOMMU and CONFIG_IRQ_REMAP. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: yinghai@kernel.org Cc: youquan.song@intel.com Cc: joerg.roedel@amd.com Cc: tony.luck@intel.com Cc: dwmw2@infradead.org Link: http://lkml.kernel.org/r/20110824001456.558630224@sbsiddha-desk.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
* agp/intel: add Ivy Bridge supportJesse Barnes2011-05-131-0/+10
| | | | | | | | Just use the Sandy Bridge routines. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* agp/intel: Experiment with a 855GM GWB bitChris Wilson2011-02-221-35/+21
| | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27187 Tested-by: Thorsten Vollmer <thorsten@thvo.de> (DFI-ACP G5M150-N w/852GME) Tested-by: Moritz Brunner <2points@gmx.org> (Asus M2400N/i855GM) Tested-by: Indan Zupancic <indan@nul.nu> (Thinkpad X40/855GM rev 02) Tested-by: Eric Anholt <eric@anholt.net> (865G) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915,agp/intel: Do not clear stolen entriesChris Wilson2011-01-241-10/+9
| | | | | | | | | | | | | We can only utilize the stolen portion of the GTT if we are in sole charge of the hardware. This is only true if using GEM and KMS, otherwise VESA continues to access stolen memory. Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Frederic Weisbecker <fweisbec@gmail.com> Tested-by: Jiri Olsa <jolsa@redhat.com> Tested-by: Frederic Weisbecker <fweisbec@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* agp/intel: Fix device names of i845 and 845GOswald Buddenhagen2011-01-141-1/+1
| | | | | | | | They got mixed up when the switch was converted to a table in 2007. Signed-off-by: Oswald Buddenhagen <ossi@kde.org> [ickle: minor changes for 2.6.37+] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* i915/gtt: fix ordering causing DMAR errors on object teardown.Dave Airlie2011-01-121-2/+2
| | | | | | | | | | | Previous to the last GTT rework we always rewrote the GTT then unmapped the object, somehow this got reversed in the rework in 2.6.37-rc5 timeframe. This fix needs to go to stable in an alternate form since the code changed. This fixes DMAR reports on my Ironlake HP2540p. Signed-off-by: Dave Airlie <airlied@redhat.com>
* i915/gtt: fix ordering issues with status setup and DMARDave Airlie2011-01-121-2/+2
| | | | | | | | This code was setting up the status page before setting the DMAR-is-on-bit, so we were getting DMAR errors on the status page. Reverse the two bits of init code to the correct result. Signed-off-by: Dave Airlie <airlied@redhat.com>
* agp/intel: Flush the chipset write buffers when changing GTT baseChris Wilson2011-01-111-0/+9
| | | | | | | | | | Flush the chipset write buffers before and after adjusting the GTT base register, just in case. We only modify this value upon initialisation (boot and resume) so there should be no outstanding writes, however there are always those persistent PGTBL_ER that keep getting reported upon resume. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-141-2/+9
|\
| * agp/intel: Fix missed cached memory flags setting in i965_write_entry()Chris Wilson2010-12-141-2/+9
| | | | | | | | | | | | | | | | This fixes regression from a6963596a13e62f8e65b1cf3403a330ff2db407c, that missed to set cached memory type in GTT entry. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-051-2/+4
|\| | | | | | | | | | | | | | | Immediate merge for the conflicting introduction of HAS_COHERENT_RINGS. Conflicts: drivers/gpu/drm/i915/i915_dma.c include/drm/i915_drm.h
| * agp/intel: Fix wrong kunmap in i830_cleanup()Takashi Iwai2010-12-051-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add a missing NULL check and fix the wrong address passed to kunmap() in i830_cleanup(). Cc: stable@kernel.org Signed-off-by: Takashi Iwai <tiwai@suse.de> [danvet: added cc stable] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * agp/intel: fix cache control for sandybridgeZhenyu Wang2010-11-041-2/+2
| | | | | | | | | | | | | | | | | | This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * agp/intel: restore cache behavior on sandybridgeZhenyu Wang2010-11-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: Remove duplicate constChris Wilson2010-11-231-1/+1
| | | | | | | | | | | | drivers/char/agp/intel-gtt.c:340:48: warning: duplicate const Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | intel-gtt: export api for drm/i915Daniel Vetter2010-11-231-52/+68
| | | | | | | | | | | | | | | | Just some minor shuffling to get rid of any agp traces in the exported functions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp: kill agp_flush_chipset and corresponding ioctlDaniel Vetter2010-11-231-6/+0
| | | | | | | | | | | | | | | | | | The intel drm calls the chipset functions now directly. Userspace never called the corresponding ioctl, hence it can be killed, too. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915/gtt: call chipset flush directlyDaniel Vetter2010-11-231-0/+7
| | | | | | | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915|intel-gtt: consolidate intel-gtt.h headersDaniel Vetter2010-11-231-5/+0
| | | | | | | | | | | | | | ... and a few other defines. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | intel-gtt: fold i81x-only dcache support into the generic driverDaniel Vetter2010-11-231-89/+61
| | | | | | | | | | | | | | Now the intel-gtt.c rewrite is complete! Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | intel-gtt: switch i81x to the common initialization helpersDaniel Vetter2010-11-231-127/+71
| | | | | | | | | | | | | | | | Still a separate agp_bridge_driver because of the i81x-only dedicated vram support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | intel-gtt: switch i81x to the write_entry helpersDaniel Vetter2010-11-231-92/+60
| | | | | | | | | | | | | | | | | | Initialization is still done with the old code with a few added things sprinkled in to make the intel_fake_agp helper functions work. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | intel-gtt: kill unneeded sandybridge memory typesDaniel Vetter2010-11-231-6/+0
| | | | | | | | | | | | | | Used for the now dead agp type_to_mask stuff. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | intel-gtt: drop dcache support for i830 and laterDaniel Vetter2010-11-231-7/+1
| | | | | | | | | | | | | | | | i830_check_flags already disallows it, so no need to implement it in the write_entry function. Seems to be a remnant from i810 support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: Remove confusion of stolen entries not stolen memoryChris Wilson2010-11-231-33/+7
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: Remove the artificial cap on stolen sizeChris Wilson2010-11-231-13/+3
| | | | | | | | | | | | | | Now that the stolen memory does not also steal entries from the GTT, we can use all the memory the BIOS set aside for the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: restore cache behavior on sandybridgeZhenyu Wang2010-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: fix cache control for sandybridgeZhenyu Wang2010-11-021-2/+2
| | | | | | | | | | | | | | | | This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: the GMCH is always enabled for integrated processor graphicsChris Wilson2010-10-311-16/+27
| | | | | | | | | | | | | | | | | | | | ... and trying to set the bit is ineffectual. Fixes the regression from e380f60 which detected that we were trying to do undefined operations on the I830_GMCH_CTRL. Reported-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: Sandybridge doesn't require GMCH enablingChris Wilson2010-10-291-7/+30
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | intel-gtt: maximize ggtt size on platforms that support thisDaniel Vetter2010-10-271-26/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On VT-d supporting platforms the GGTT is allocated in a stolen mem section separate from graphcis stolen mem. The GMCH register contains a bitfield specifying the size of that region. Docs suggest that this region can only be used for GGTT and PPGTT. Hence ensure that the PPGTT is disabled and use the complete area for the GGTT. Unfortunately the graphics core on G33/Pineview can't cope with really large GTTs and the BIOS usually enables the maximum of 512MB. So don't bother with maximizing the GTT on these platforms. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | intel-gtt: save PGETBL_CTL later in the setup processDaniel Vetter2010-10-271-7/+7
|/ | | | | | | | | | | | ... and switch to a more classical store-reg-on-suspend, restore-on-resume way of doing things. Obviously this is just preparation for the future, the code is not there at all, yet. This is needed because the next patch adjusts this register and everything in it (not just the pagetable address) needs to be restored on resume. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* agp/intel: Restore valid PTE bit for Sandybridge after bdd3072Chris Wilson2010-10-221-3/+3
| | | | | | | In cleaning up the mask functions in bdd3072, the setting of the PTE valid bit was dropped for Sandybridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* some clean up to intel-gtt.cJan Beulich2010-09-241-2/+1
| | | | | | | | | | | | | | | | In commit e517a5e97080bbe52857bd0d7df9b66602d53c4d the call to map_page_into_agp() got removed from intel_i830_setup_flush(), but the counterpart call from intel_i830_fini_flush() to unmap_page_from_agp() was left in place. Additionally, the page allocated here never gets its physical address used for sending to hardware, so there's no need to allocate it with GFP_DMA32. Nor is __GFP_ZERO really necessary, as the page is used only to store data to force flushing of some internal processor state. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* intel-gtt add a cleanup function for chipset specific stuffDaniel Vetter2010-09-211-8/+31
| | | | | | | | The old code didn't clean up the i830 chipset flush page. And it looks nicer. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* intel-gtt: store the dma mask size in intel_gtt_driverDaniel Vetter2010-09-211-7/+11
| | | | | | | | Storing this explicitly makes for clearer code and hopefully less further confusion. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* intel-gtt: clean up gtt size reportingDaniel Vetter2010-09-211-1/+5
| | | | | | | | Consolidate everything in intel-gtt.c and also kill the export of intel_max_stolen. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* intel-gtt: consolidate fake_agp driver structsDaniel Vetter2010-09-211-131/+39
| | | | | | | They're now all the same. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* intel-gtt: move chipset flush to the gtt driver structDaniel Vetter2010-09-211-7/+21
| | | | | | | This is the last differentiator between the different fake agp drivers. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* intel-gtt: kill mask_memory functionsDaniel Vetter2010-09-211-92/+13
| | | | | | | | That indirection mess can now go. Add a dummy i81x gtt_driver to avoid a NULL pointer check. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* intel-gtt: generic (insert|remove)_entries for sandybridgeDaniel Vetter2010-09-211-136/+8
| | | | | | | | Like before, but now with the added bonus of being able to kill quite a bit of no-longer userful code (the old dmar support stuff). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-17 15:56:24 +0000