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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-3017-101/+17
| | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
*-. Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' ↵Stephen Boyd2019-05-0715-154/+840
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'clk-spdx' into clk-next - Support for STM32F769 - Rework AT91 sckc DT bindings - Fix slow RC oscillator issue on sama5d3 - AT91 sam9x60 PMC support - SiFive FU540 PRCI and PLL support * clk-stm32f4: clk: stm32mp1: Add ddrperfm clock clk: stm32: Introduce clocks of STM32F769 board * clk-tegra: clk: tegra: divider: Mark Memory Controller clock as read-only clk: tegra: emc: Replace BUG() with WARN_ONCE() clk: tegra: emc: Fix EMC max-rate clamping clk: tegra: emc: Support multiple RAM codes clk: tegra: emc: Don't enable EMC clock manually clk: tegra124: Remove lock-enable bit from PLLM clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider clk: tegra: Don't enable already enabled PLLs * clk-at91: clk: at91: Mark struct clk_range as const clk: at91: add sam9x60 pmc driver dt-bindings: clk: at91: add bindings for SAM9X60 pmc clk: at91: add sam9x60 PLL driver clk: at91: master: Add sam9x60 support clk: at91: usb: Add sam9x60 support clk: at91: allow configuring generated PCR layout clk: at91: allow configuring peripheral PCR layout clk: at91: sckc: handle different RC startup time clk: at91: modernize sckc binding dt-bindings: clock: at91: new sckc bindings * clk-sifive-fu540: clk: sifive: add a driver for the SiFive FU540 PRCI IP block clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver * clk-spdx: clk: sunxi-ng: Use the correct style for SPDX License Identifier clk: sprd: Use the correct style for SPDX License Identifier clk: renesas: Use the correct style for SPDX License Identifier clk: qcom: Use the correct style for SPDX License Identifier clk: davinci: Use the correct style for SPDX License Identifier clk: actions: Use the correct style for SPDX License Identifier
| | * clk: at91: Mark struct clk_range as constStephen Boyd2019-04-257-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | It's just some static data that doesn't get changed after being used. Mark it const everywhere. Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add sam9x60 pmc driverAlexandre Belloni2019-04-252-0/+308
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the PMC clocks of the sam9c60. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Staticize spinlock] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add sam9x60 PLL driverAlexandre Belloni2019-04-253-0/+337
| | | | | | | | | | | | | | | | | | | | | | | | The PLLs on the sam9x60 (PLLA and USB PLL) use a different register set and programming model than the previous SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: master: Add sam9x60 supportAlexandre Belloni2019-04-252-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | The sam9x60 cpu clock is located at a different offset but is otherwise similar to the master clock. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: usb: Add sam9x60 supportAlexandre Belloni2019-04-252-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | The sam9x60 USB clock supports four different parents, ensure they can be selected. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: allow configuring generated PCR layoutAlexandre Belloni2019-04-254-24/+29
| | | | | | | | | | | | | | | | | | | | | | | | The PCR register layout for GCLKCSS is changing for the future SoCs, allow configuring it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: allow configuring peripheral PCR layoutAlexandre Belloni2019-04-256-22/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCR register actually changed layout for each SoC. By chance, this didn't have impact on sama5d[2-4] support but since sama5d3, PID is seven bits wide and sama5d4 and sama5d2 don't have DIV. For the DT backward compatibility, keep the layout as is. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: sckc: handle different RC startup timeAlexandre Belloni2019-04-251-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | The sama5d3 slow RC oscillator as a different startup time than all the previous SoCs. Handle that using its own compatible. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: modernize sckc bindingAlexandre Belloni2019-04-251-89/+36
| |/ | | | | | | | | | | | | | | | | | | | | Remove the need for child nodes in the sckc binding and register the whole sckc tree (3 clocks in total) from the sckc node. DT backward compatibility is kept by looking for properties in child nodes when they are not present in the sckc node. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* / clk: at91: fix programmable clock for sama5d2Matthias Wieloch2019-03-183-15/+54
|/ | | | | | | | | | | | | | The prescaler formula of the programmable clock has changed for sama5d2. Update the driver accordingly. Fixes: a2038077de9a ("clk: at91: add sama5d2 PMC driver") Cc: <stable@vger.kernel.org> # v4.20+ Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [nicolas.ferre@microchip.com: adapt the prescaler range, fix clk_programmable_recalc_rate, split patch] Signed-off-by: Matthias Wieloch <matthias.wieloch@few-bauer.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge branch 'clk-at91' into clk-nextStephen Boyd2019-03-083-5/+10
|\ | | | | | | | | | | | | * clk-at91: clk: at91: programmable: remove unneeded register read clk: at91: optimize clk_round_rate() for AUDIO_PLL clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2
| * clk: at91: programmable: remove unneeded register readNicolas Ferre2019-02-251-3/+0
| | | | | | | | | | | | | | | | | | This register read is a leftover of a previous read/modify/write. We now use regmap_update_bits(), so we don't need it anymore. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: at91: optimize clk_round_rate() for AUDIO_PLLMichał Mirosław2019-02-221-1/+8
| | | | | | | | | | | | | | | | | | | | | | Stop the search for parent rate when exact match is found. This makes for 3 clk_round_rate() calls instead of 64 of them on SAMA5D2-based board when searching for 12.288MHz clock. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2Michał Mirosław2019-01-091-1/+2
| | | | | | | | | | | | | | | | Datasheet for SAMA5D2x mentions 6 sources for PCKx, the last being AUDIOPLL. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: at91: fix masterck nameAlexandre Belloni2019-02-203-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The master clock is actually named masterck earlier in the driver. Having "mck" in the parent list means that it can never be selected. Fixes: 1eabdc2f9dd8 ("clk: at91: add at91sam9x5 PMCs driver") Fixes: a2038077de9a ("clk: at91: add sama5d2 PMC driver") Fixes: 084b696bb509 ("clk: at91: add sama5d4 pmc driver") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: <stable@vger.kernel.org> # v4.20+ Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: at91: fix at91sam9x5 peripheral clock numberAlexandre Belloni2019-02-201-2/+1
|/ | | | | | | | | | | | nck() looks at the last id in an array and unfortunately, at91sam9x35_periphck has a sentinel, hence the id is 0 and the calculated number of peripheral clocks is 1 instead of a maximum of 31. Fixes: 1eabdc2f9dd8 ("clk: at91: add at91sam9x5 PMCs driver") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: <stable@vger.kernel.org> # v4.20+ Signed-off-by: Stephen Boyd <sboyd@kernel.org>
*-. Merge branches 'clk-actions-reset', 'clk-imx7-init-critical', 'clk-mmp2-ids' ↵Stephen Boyd2018-10-1824-990/+2870
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'clk-at91-pmc-rework' into clk-next - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs - Rework at91 PMC clock driver for new DT bindings * clk-actions-reset: clk: actions: Add Actions Semi S900 SoC Reset Management Unit support clk: actions: Add Actions Semi S700 SoC Reset Management Unit support clk: actions: Add Actions Semi Owl SoCs Reset Management Unit support dt-bindings: reset: Add binding constants for Actions Semi S900 RMU dt-bindings: reset: Add binding constants for Actions Semi S700 RMU dt-bindings: clock: Add reset controller bindings for Actions Semi Owl SoCs clk: actions: Cache regmap info in private clock descriptor * clk-imx7-init-critical: clk: imx7d: remove CLK_IS_CRITICAL flag for arm_a7_root_clk clk: imx: cpu clock should be always critical clk: imx: imx7d: remove clks_init_on array clk: imx: imx7d: remove unnecessary clocks from clks_init_on array * clk-mmp2-ids: clk: mmp2: fix the clock id for sdh2_clk and sdh3_clk * clk-at91-pmc-rework: clk: at91: move DT compatibility code to its own file clk: at91: add at91sam9rl PMC driver clk: at91: add at91sam9x5 PMCs driver clk: at91: add at91sam9260 PMC driver clk: at91: add sama5d2 PMC driver clk: at91: add sama5d4 pmc driver clk: at91: add new DT lookup function dt-bindings: clk: at91: Document new PMC binding clk: at91: add pmc_data struct and helpers clk: at91: allow clock registration from C code clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated() clk: at91: audio-pll: separate registration from DT parsing clk: at91: h32mx: separate registration from DT parsing clk: at91: generated: SSCs don't have a gclk clk: at91: audio-pll: fix audio pmc type
| | * clk: at91: move DT compatibility code to its own fileAlexandre Belloni2018-10-1717-944/+962
| | | | | | | | | | | | | | | | | | | | | | | | Move all the DT backward compatibility code to its own file so it can be deleted later. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add at91sam9rl PMC driverAlexandre Belloni2018-10-172-1/+172
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the PMC clocks of the at91sam9rl SoC. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Make i signed to fix signedness bug] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add at91sam9x5 PMCs driverAlexandre Belloni2018-10-172-1/+310
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the PMC clocks of the at91sam9x5 SoCs Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Make i signed to fix signedness bug] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add at91sam9260 PMC driverAlexandre Belloni2018-10-172-0/+495
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the PMC clocks of the at91sam9260, at91sam9261, at91am9263 and at91sam9g20 SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Make i signed to fix signedness bug] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add sama5d2 PMC driverAlexandre Belloni2018-10-172-0/+337
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the PMC clocks of the sama5d2 Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Make i signed to fix signedness bug] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add sama5d4 pmc driverAlexandre Belloni2018-10-172-0/+265
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the PMC clocks of the sama5d4 Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Make i signed to fix signedness bug] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add new DT lookup functionAlexandre Belloni2018-10-171-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new DT lookup function to lookup for PMC clocks. Note that the #ifndef AT91_PMC_MOSCS section will be removed once all the platforms are converted. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: add pmc_data struct and helpersAlexandre Belloni2018-10-172-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | Add a new strut to handle references to all the PMC clocks and implement allocation/free helpers. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: allow clock registration from C codeAlexandre Belloni2018-10-1714-59/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove static keyword to allow functions to be used from other units. Also move some struct and function declarations to pmc.h Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Include pmc.h] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated()Alexandre Belloni2018-10-171-17/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it easier to do it from code that is not parsing device tree. Also, this fixes an issue where the resulting clk_hw can be dereferenced before being tested for error. Fixes: 1a1a36d72e3d ("clk: at91: clk-generated: make gclk determine audio_pll rate") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: audio-pll: separate registration from DT parsingAlexandre Belloni2018-10-171-38/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | Separate registration out of of_sama5d2_clk_audio_pll*_setup to allow other code to use it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Include pmc.h] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: h32mx: separate registration from DT parsingAlexandre Belloni2018-10-171-13/+27
| | | | | | | | | | | | | | | | | | | | | | | | Separate registration out of of_sama5d4_clk_h32mx_setup to allow other code to use it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: generated: SSCs don't have a gclkAlexandre Belloni2018-10-171-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | As the SSCs don't have gclk, don't check for their ID to allow them to set the audio pll rate. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: at91: audio-pll: fix audio pmc typeAlexandre Belloni2018-10-171-1/+1
| |/ | | | | | | | | | | | | | | | | | | The allocation for the audio pmc is using the size of struct clk_audio_pad instead of struct clk_audio_pmc. This works fine because the former is larger than the latter but it is safer to be correct. Fixes: ("0865805d82d4 clk: at91: add audio pll clock drivers") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* / clk: at91: Fix division by zero in PLL recalc_rate()Ronald Wahl2018-10-161-0/+3
|/ | | | | | | | | | | | | Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL and DIV values") removed a check that prevents a division by zero. This now causes a stacktrace when booting the kernel on a at91 platform if the PLL DIV register contains zero. This commit reintroduces this check. Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...") Cc: <stable@vger.kernel.org> Signed-off-by: Ronald Wahl <rwahl@gmx.de> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: at91: add I2S clock mux driverCodrin Ciubotariu2018-07-062-0/+117
| | | | | | | | | | This driver is a simple muxing driver that controls the I2S's clock input by using syscon/regmap to change the parent. The available inputs can be peripheral clock and generated clock. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> [sboyd@kernel.org: Fix SPDX tag comment style] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: at91: PLL recalc_rate() now using cached MUL and DIV valuesMarcin Ziemianowicz2018-05-151-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a USB device is connected to the USB host port on the SAM9N12 then you get "-62" error which seems to indicate USB replies from the device are timing out. Based on a logic sniffer, I saw the USB bus was running at half speed. The PLL code uses cached MUL and DIV values which get set in set_rate() and applied in prepare(), but the recalc_rate() function instead queries the hardware instead of using these cached values. Therefore, if recalc_rate() is called between a set_rate() and prepare(), the wrong frequency is calculated and later the USB clock divider for the SAM9N12 SOC will be configured for an incorrect clock. In my case, the PLL hardware was set to 96 Mhz before the OHCI driver loads, and therefore the usb clock divider was being set to /2 even though the OHCI driver set the PLL to 48 Mhz. As an alternative explanation, I noticed this was fixed in the past by 87e2ed338f1b ("clk: at91: fix recalc_rate implementation of PLL driver") but the bug was later re-introduced by 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally"). Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally) Cc: <stable@vger.kernel.org> Signed-off-by: Marcin Ziemianowicz <marcin@ziemianowicz.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: at91: pmc: Support backup for programmable clocksRomain Izard2017-12-213-0/+39
| | | | | | | | | | | | When an AT91 programmable clock is declared in the device tree, register it into the Power Management Controller driver. On entering suspend mode, the driver saves and restores the Programmable Clock registers to support the backup mode for these clocks. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: pmc: Save SCSR during suspendRomain Izard2017-12-211-2/+2
| | | | | | | | | | | | | | | | | The contents of the System Clock Status Register (SCSR) needs to be restored into the System Clock Enable Register (SCER). As the bootloader will restore some clocks by itself, the issue can be missed as only the USB controller, the LCD controller, the Image Sensor controller and the programmable clocks will be impacted. Fix the obvious typo in the suspend/resume code, as the IMR register does not need to be saved twice. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: pmc: Wait for clocks when resumingRomain Izard2017-12-211-8/+16
| | | | | | | | | | | | Wait for the syncronization of all clocks when resuming, not only the UPLL clock. Do not use regmap_read_poll_timeout, as it will call BUG() when interrupts are masked, which is the case in here. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-11-171-14/+81
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have two changes to the core framework this time around. The first being a large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Summary: Core: - runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - runtime PM support for Samsung exynos5433/exynos4412 providers - removal of clkdev aliases on Samsung SoCs - convert clk-gpio to use gpio descriptors - various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - support for the second display unit clock on Renesas RZ/G1E - suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - new clock ids for Rockchip rk3188 and rk3368 SoCs - various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: stm32h7: fix test of clock config clk: pxa: fix building on older compilers clk: sunxi-ng: a83t: Fix i2c buses bits clk: ti: dra7-atl-clock: fix child-node lookups clk: qcom: common: fix legacy board-clock registration clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: kona-setup: Delete error messages for failed memory allocations ARC: clk: fix spelling mistake: "configurarion" -> "configuration" clk: cdce925: remove redundant check for non-null parent_name clk: versatile: Improve sizeof() usage clk: versatile: Delete error messages for failed memory allocations clk: ux500: Improve sizeof() usage clk: ux500: Delete error messages for failed memory allocations clk: spear: Delete error messages for failed memory allocations clk: ti: Delete error messages for failed memory allocations clk: mmp: Adjust checks for NULL pointers ...
| * clk: at91: utmi: set the mainck rateLudovic Desroches2017-11-011-14/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Ingo van Lil <inguin@gmx.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: at91: clk-generated: make gclk determine audio_pll rateQuentin Schulz2017-09-011-6/+57
| | | | | | | | | | | | | | | | | | | | This allows gclk to determine audio_pll rate and set the parent rate accordingly. However, there are multiple children clocks that could technically change the rate of audio_pll (via gck). With the rate locking, the first consumer to enable the clock will be the one definitely setting the rate of the clock. Since audio IPs are most likely to request the same rate, we enforce that the only clks able to modify gck rate are those of audio IPs. To remain consistent, we deny other clocks to be children of audio_pll. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: clk-generated: create function to find best_diffQuentin Schulz2017-09-011-14/+27
| | | | | | | | | | | | | The way to find the best_diff and do the appropriate process afterwards can be re-used. This patch prepares the driver for an upcoming patch that will allow clk_generated to determine the rate of the audio_pll. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: add audio pll clock driversQuentin Schulz2017-09-012-0/+537
| | | | | | | | | | | | | | | | | | | This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications. The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formulas, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: clk-generated: remove useless divisor loopQuentin Schulz2017-09-011-13/+12
| | | | | | | | | | | | | | | | | The driver requests the current clk rate of each of its parent clocks to decide whether a clock rate is suitable or not. It does not request determine_rate from a parent clock which could request a rate change in parent clock (i.e. there is no parent rate propagation). We know the rate we want (passed along req argument of the function) and the parent clock rate, thus we know the closest rounded divisor, we don't need to iterate over the available divisors to find the best one for a given clock. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: Add sama5d2 suspend/resumeAlexandre Belloni2017-06-294-1/+140
| | | | | | | | | On sama5d2, VDD core maybe be cut while in suspend. This means registers will be lost. Ensure they are saved and restored properly. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: fix clk-generated compilationAlexandre Belloni2017-06-051-0/+1
| | | | | | | Fix missing } Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: fix clk-generated parentingAlexandre Belloni2017-06-011-2/+1
| | | | | | | | | | clk_generated_startup is called after clk_hw_register. So the first call to get_parent will not have the correct value (i.e. 0) and because this is cached, it may never be updated. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Fixes: df70aeef6083 ("clk: at91: add generated clock driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()Markus Elfring2017-04-211-3/+3
| | | | | | | | | | | Multiplications for the size determination of memory allocations indicated that array data structures should be processed. Thus use the corresponding function "kcalloc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 13:45:05 +0000