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* clk: hisilicon: fix warning from smatchZhangfei Gao2014-03-201-8/+7
| | | | | | | | | drivers/clk/hisilicon/clk-hi3620.c:338 mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'clk-hisi' of ↵Mike Turquette2014-03-195-39/+128
|\ | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
| * clk: hisi: remove static variableHaojian Zhuang2014-03-194-42/+72
| | | | | | | | | | | | | | Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * clk: hip04: add clock driverHaojian Zhuang2014-03-192-1/+58
| | | | | | | | | | | | Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * clk: hisi: assign missing clk to tableHaojian Zhuang2014-03-191-0/+2
| | | | | | | | | | | | The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | clk: hisilicon: add hi3620_mmc_clksZhangfei Gao2014-02-261-0/+274
|/ | | | | | | | | | | Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: hi3620: add gate clock flagHaojian Zhuang2013-12-111-59/+59
| | | | | | Add missing CLK_SET_RATE_PARENT flag for gate clock. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* clk: hi3620: fix wrong flags on dividerHaojian Zhuang2013-12-111-11/+11
| | | | | | | The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not CLK_MUX_HIWORD_MASK. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* clk: hisilicon: add common clock supportHaojian Zhuang2013-12-045-0/+651
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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