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* clk: mvebu: add Marvell Armada 39x driverThomas Petazzoni2015-03-043-0/+161
| | | | | | | | | | | | | This commit adds a new clock driver for the Marvell Armada 39x family of processors. This driver is fairly similar to the ones already used on other Marvell EBU processors, with the following main differences: * Different set of ratios * Different set of core clocks * Configurable reference clock in frequency Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* clk: mvebu: extend common code to allow an optional refclkThomas Petazzoni2015-03-042-0/+18
| | | | | | | | | | | | | | | | The Armada 39x, contrary to its predecessor, has a configurable reference clock frequency, of either 25 Mhz, or 40 Mhz. For the previous SoCs, it was fixed to 25 Mhz and described directly as such in the Device Tree. For Armada 39x, we need to read certain registers to know whether the frequency is 25 or 40 Mhz. Therefore, this commit extends the common mvebu clock code to allow the SoC-specific code to say it wants to register a reference clock, by giving a non-NULL ->get_refclk_freq() function pointer in its coreclk_soc_desc structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* clk: mvebu: add suspend/resume for gatable clocksThomas Petazzoni2014-11-301-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds suspend/resume support for the gatable clock driver used on Marvell EBU platforms. When getting out of suspend, the Marvell EBU platforms go through the bootloader, which re-enables all gatable clocks. However, upon resume, the clock framework will not disable again all gatable clocks that are not used. Therefore, if the clock driver does not save/restore the state of the gatable clocks, all gatable clocks that are not claimed by any device driver will remain enabled after a resume. This is why this driver saves and restores the state of those clocks. Since clocks aren't real devices, we don't have the normal ->suspend() and ->resume() of the device model, and have to use the ->suspend() and ->resume() hooks of the syscore_ops mechanism. This mechanism has the unfortunate idea of not providing a way of passing private data, which requires us to change the driver to make the assumption that there is only once instance of the gatable clock control structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-kernel@vger.kernel.org Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Merge tag 'clk-mvebu-3.18-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2014-10-032-5/+5
|\ | | | | | | | | | | | | | | | | clk-next clock mvebu changes for v3.18 (round 2) - armada 370/375 - Fix SSCG node lookup
| * clk: mvebu: fix sscg node lookupThomas Petazzoni2014-09-162-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 15917b16022427c53755abff4dc7051f3076dd7a ("clk: mvebu: Fix clk frequency value if SSCG is enabled") introduced some logic in the common mvebu clock code to adjust the clock frequency according to the configuration of the SSCG. In order to do this, it looks up for a DT node called "sscg" and maps it before accessing the SSCG configuration register. However, the lookup is currently done using: sscg_np = of_find_node_by_name(np, "sscg"); where "np" is a pointer to the DT node of the clock for which we are calculating the adjusted frequency. This means that if the "sscg" node is *after* the clock node in the Device Tree, it works fine (and that's the case for Armada 370). However, if it turns out that the "sscg" node is *before* the clock node in the Device Tree, it won't work because the sscg node will not be found. What we really want here is a search of the entire Device Tree, not only starting from the clock node, so instead of passing "np" as first argument of of_find_node_by_name(), we simply need to pass NULL. Passing a non-NULL argument is typically used in a loop, so that the search for the next matching node starts right after the node that was matched. This makes the "np" argument to the kirkwood_fix_sscg_deviation() function unnecessary, which leads to further cleanups. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Fixes: 15917b1602242 ("clk: mvebu: Fix clk frequency value if SSCG is enabled") Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1410880503-2322-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge tag 'clk-mvebu-3.18' of git://git.infradead.org/linux-mvebu into clk-nextMike Turquette2014-09-264-2/+99
|\| | | | | | | | | | | | | clock changes for mvebu for v3.18 - correct timer drift caused by SSCG deviation - fix typo in comment
| * clk: mvebu: armada-375: Fix the description of the SAR in the commentGregory CLEMENT2014-09-091-2/+2
| | | | | | | | | | | | | | | | | | | | For dealing with the code we use the SAR1 and not the SAR0. The code was correct, and now the comments too. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Leigh Brown <leigh@solinno.co.uk> Link: https://lkml.kernel.org/r/1409645719-20003-5-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * clk: mvebu: armada-370: Fix timer drift caused by the SSCG deviationGregory CLEMENT2014-09-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit activates the SSCG deviation correction for the Armada 370. It uses the optional function introduced by the commit "clk: mvebu: Fix clk frequency value if SSCG is enabled". Without this fix the deviation measured on a Mirabox was of a few second each hour, whereas with this fix it was reduced at around 50ppm (around 4s per day). Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Leigh Brown <leigh@solinno.co.uk> Link: https://lkml.kernel.org/r/1409645719-20003-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * clk: mvebu: Fix clk frequency value if SSCG is enabledGregory CLEMENT2014-09-092-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the SSCG (Spread Spectrum Clock Generator) is enabled, it shifts the frequency of the clock. The percentage is no more than 1% but when the clock is used for a timer it leads to a clock drift. This patch allows to correct the affected clock when the SSCG is enabled. The check is done in an new optional function related to each SoC: is_sscg_enabled(). The fix is done with the other new optional function related to each SoC: fix_sscg_deviation. If one these functions are not present then no correction is done on the clock frequency. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Leigh Brown <leigh@solinno.co.uk> Link: https://lkml.kernel.org/r/1409645719-20003-2-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | cpufreq: kirkwood: use the powersave multiplexerMike Turquette2014-09-021-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The powersave clock acts like a multiplexer for the cpu, selecting either the clock signal derived from the cpu pll or from the ddr clock. This patch changes powersave from a gate clock to a mux clock to better reflect this behavior. This is a cleaner approach whereby the frequency of the cpu always matches the rate of powersave_clk. The cpufreq driver for the kirkwood platform no longer must parse this behavior out of various calls to clk_enable and clk_disable, but can instead simply select the parent cpu it wants when changing rate. Likewise when requesting the cpu rate we need only query powersave_clk's rate through the usual call to clk_get_rate. The new clock data and corresponding changes to the cpufreq driver are combined into this single commit to avoid a git bisect issue where this cpufreq driver fails to work properly between the commit that updates the kirkwood clock driver and the commit that changes how the cpufreq driver uses that clock. Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Tested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: mvebu: powersave clock is a multiplexerMike Turquette2014-09-011-0/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kirkwood is unique among the mvebu SoCs for having a clock multiplexer that feeds into the cpu. This multiplexer can select either the cpu pll or the ddr clock as its input signal, allowing for a choice between performance and power savings. This patch introduces the code needed to register the clock multiplexer on Kirkwood SoCs but does not include the clock data to actually register the clock. That will be done in a follow-up patch which is necessary to prevent breaking git bisect. Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: mvebu: share locks between gate clocksMike Turquette2014-09-012-3/+8
|/ | | | | | | | | | | | Refactor mvebu_clk_gating_setup() to use a common spinlock instead of a unique lock for every instance of a struct clk_gating_ctrl object. This will be used later for a separate mux clock type that shares a register with gate clock types and needs to use the same lock to protect access to the register. Cc: Andrew Lunn <andrew@lunn.ch> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mvebu: extend clk-cpu for dynamic frequency scalingThomas Petazzoni2014-07-161-5/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit extends the existing clk-cpu driver used on Marvell Armada XP platforms to support the dynamic frequency scaling of the CPU clock. Non-dynamic frequency change was already supported (and used before secondary CPUs are started), but the dynamic frequency change requires a completely different procedure. In order to achieve this, the clk_cpu_set_rate() function is reworked to handle two separate cases: - The case where the clock is enabled, which is the new dynamic frequency change code, implemented in clk_cpu_on_set_rate(). This part will be used for cpufreq activities. - The case where the clock is disabled, which is the existing frequency change code, moved in clk_cpu_off_set_rate(). This part is already used to set the clock frequency of the secondary CPUs before starting them. In order to implement the dynamic frequency change function, we need to access the PMU DFS registers, which are outside the currently mapped "Clock Complex" registers, so a new area of registers is now mapped. This affects the Device Tree binding, but we are careful to do it in a backward-compatible way (by allowing the second pair of registers to be non-existent, and in this case, ensuring clk_cpu_on_set_rate() returns an error). Note that technically speaking, the clk_cpu_on_set_rate() does not do the entire procedure needed to change the frequency dynamically, as it involves touching a number of PMSU registers. This is done through a clock notifier registered by the PMSU driver in followup commits. Cc: <devicetree@vger.kernel.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1404920715-19834-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: add Orion5x clock driverThomas Petazzoni2014-04-263-0/+215
| | | | | | | | | | | | | | | | This commit adds a core clock driver for the Orion5x SoC, with support for the tclk, the CPU frequency and the DDR frequency. All the details about the Sample-At-Reset register were extracted from the U-Boot sources for Orion5x. Note that Orion5x does not have gatable clocks, so this core clock driver is sufficient to support clocking on Orion5x platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1398202002-28530-5-git-send-email-thomas.petazzoni@free-electrons.com Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2014-03-181-1/+24
|\ | | | | | | | | | | | | | | | | | | | | | | clk-next-mvebu clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
| * clk: mvebu: Support Armada 380 SoC on the core divider clockEzequiel Garcia2014-03-131-0/+23
| | | | | | | | | | | | | | | | | | | | This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * clk: mvebu: Fix ratio register offset on A375 SoCEzequiel Garcia2014-03-131-1/+1
| | | | | | | | | | | | | | | | | | This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-02-244-50/+44
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| * clk: mvebu: kirkwood: maintain clock init orderSebastian Hesselbarth2014-02-061-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * clk: mvebu: dove: maintain clock init orderSebastian Hesselbarth2014-02-061-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * clk: mvebu: armada-xp: maintain clock init orderSebastian Hesselbarth2014-02-061-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * clk: mvebu: armada-370: maintain clock init orderSebastian Hesselbarth2014-02-061-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | clk: mvebu: add clock support for Armada 380/385Gregory CLEMENT2014-02-173-0/+172
| | | | | | | | | | | | | | | | | | Add the clock support for the new SoCs Armada 380 and Armada 385: core clocks and gating clocks. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | clk: mvebu: add clock support for Armada 375Gregory CLEMENT2014-02-173-0/+189
| | | | | | | | | | | | | | | | | | Add the clock support for the new SoC Armada 375: core clocks and gating clocks. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | clk: mvebu: add Armada 375 support to the corediv clock driverThomas Petazzoni2014-02-171-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for the Core Divider clocks of the Armada 375. Compared to Armada 370 and XP the Core Divider clocks of the 375 cannot be gated: only their ratio can be changed. This is reflected by the fact that the enable, disable and is_enabled clock operations are not defined, and that the enable_bit_offset field is also undefined. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | clk: mvebu: refactor corediv driver to support more SoCThomas Petazzoni2014-02-171-24/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit refactors the corediv clock driver so that it is capable of handling various SOCs that have slightly different corediv clock registers and capabilities. It introduces a clk_corediv_soc_desc structure that encapsulates all the SoC specific details. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | clk: mvebu: add a little bit of documentation about data structuresThomas Petazzoni2014-02-171-0/+17
| | | | | | | | | | | | Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | clk: mvebu: do not copy the contents of clk_corediv_descThomas Petazzoni2014-02-171-8/+8
|/ | | | | | Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: Add Core Divider clockEzequiel Garcia2013-11-243-0/+229
| | | | | | | | | | | This commit introduces a new group of clocks present in Armada 370/XP SoCs (called "Core Divider" clocks) and add a provider for them. The only clock supported for now is the NAND clock (ndclk), but the infrastructure to add the rest is already set. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mvebu: staticize of_cpu_clk_setupJisheng Zhang2013-11-241-1/+1
| | | | | | | | | | | This symbol is used only in this file. The patch fix the following sparse warning: warning: symbol 'of_cpu_clk_setup' was not declared. Should it be static? Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: armada-370: fix tclk frequenciesSimon Guinot2013-10-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | This patch fixes the tclk frequency array for the Armada-370 SoC. This bug has been introduced by commit 6b72333d ("clk: mvebu: add Armada 370 SoC-centric clock init"). A wrong tclk frequency affects the following drivers: mvsdio, mvneta, i2c-mv64xxx and mvebu-devbus. This list may be incomplete. About the mvneta Ethernet driver, note that the tclk frequency is used to compute the Rx time coalescence. Then, this bug harms the coalescence configuration and also degrades the networking performances with the default values. Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: stable@vger.kernel.org Signed-off-by: Michael Turquette <mturquette@deferred.io>
* clk: kirkwood: Fix incorrect placement of __initconstSachin Kamat2013-08-271-7/+7
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: dove: Fix incorrect placement of __initconstSachin Kamat2013-08-271-6/+6
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: armada-xp: Fix incorrect placement of __initconstSachin Kamat2013-08-271-6/+6
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: armada-370: Fix incorrect placement of __initconstSachin Kamat2013-08-271-7/+7
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mvebu: add missing iounmapJisheng Zhang2013-08-232-7/+15
| | | | | | | Add missing iounmap to setup error path. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mvebu: disintegrate obsolete fileSebastian Hesselbarth2013-05-297-995/+2
| | | | | | | | | | Switch from function-centric to soc-centric clock drivers now makes a bunch of files obsolete. This deletes all files and Kconfig options that are not required anymore. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: add Armada XP SoC-centric clock initSebastian Hesselbarth2013-05-293-0/+216
| | | | | | | | | | | This is moving core clock and clock gating init for Armada XP to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: add Armada 370 SoC-centric clock initSebastian Hesselbarth2013-05-293-0/+182
| | | | | | | | | | | This is moving core clock and clock gating init for Armada 370 to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: add Kirkwood SoC-centric clock initSebastian Hesselbarth2013-05-293-0/+252
| | | | | | | | | | | This is moving core clock and clock gating init for Kirkwood to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: add Dove SoC-centric clock initSebastian Hesselbarth2013-05-293-0/+200
| | | | | | | | | | | This is moving core clock and clock gating init for Dove to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: add common clock functions for core clk and clk gatingSebastian Hesselbarth2013-05-294-0/+215
| | | | | | | | | | | | Based on the current common functions for core clocks and clock gating control, new common functions are joined in a single file. Given the opportunity, names of functions and structs are unified, and also a Kconfig entry is added. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: introduce per-clock-gate flagsSebastian Hesselbarth2013-05-291-87/+78
| | | | | | | | | | | | Clock gates found on MVEBU SoCs get registered by a common function. To allow specific SoCs to provide tweaks introduce flags to the clock gate descriptor instead of filling up the common function SoC specific tweaks. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: add more PCIe clocks for Armada XPThomas Petazzoni2013-05-201-4/+10
| | | | | | | | | | | | | | | The current revision of the datasheet only mentions the gatable clocks for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0 interfaces. After confirmation with Marvell engineers, this patch adds the missing gatable clocks for those PCIe interfaces. It also changes the name of the previously existing PCIe gatable clocks, in order to match the naming using the datasheets. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* clk: mvebu: create parent-child relation for PCIe clocks on Armada 370Thomas Petazzoni2013-05-201-2/+2
| | | | | | | | | | | The Armada 370 has two gatable clocks for each PCIe interface, and we want both of them to be enabled. We therefore make one of the two clocks a child of the other, as we did for the sataX and sataXlnk clocks on Armada XP. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Merge branch 'for-linus' of ↵Linus Torvalds2013-04-301-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial Pull trivial tree updates from Jiri Kosina: "Usual stuff, mostly comment fixes, typo fixes, printk fixes and small code cleanups" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (45 commits) mm: Convert print_symbol to %pSR gfs2: Convert print_symbol to %pSR m32r: Convert print_symbol to %pSR iostats.txt: add easy-to-find description for field 6 x86 cmpxchg.h: fix wrong comment treewide: Fix typo in printk and comments doc: devicetree: Fix various typos docbook: fix 8250 naming in device-drivers pata_pdc2027x: Fix compiler warning treewide: Fix typo in printks mei: Fix comments in drivers/misc/mei treewide: Fix typos in kernel messages pm44xx: Fix comment for "CONFIG_CPU_IDLE" doc: Fix typo "CONFIG_CGROUP_CGROUP_MEMCG_SWAP" mmzone: correct "pags" to "pages" in comment. kernel-parameters: remove outdated 'noresidual' parameter Remove spurious _H suffixes from ifdef comments sound: Remove stray pluses from Kconfig file radio-shark: Fix printk "CONFIG_LED_CLASS" doc: put proper reference to CONFIG_MODULE_SIG_ENFORCE ...
| * treewide: Fix typos in printkMasanari Iida2013-03-201-2/+2
| | | | | | | | | | | | | | Correct spelling typo in various drivers. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | clk: mvebu: Fix valid value range checking for cpu_freq_selectAxel Lin2013-04-081-2/+2
| | | | | | | | | | | | | | | | | | cpu_freq_select is used as array subscript, thus the valid value range is 0 ... ARRAY_SIZE() - 1. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up trivial merge issues]
* | clk: mvebu: Use common of_clk_init() functionJean-Francois Moine2013-04-033-42/+3
|/ | | | | | | | | The use common of_clk_init() function simplifies the clock initialization and adds handling of the DT "fixed-clock". Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed $SUBJECT to reflect correct file path]
* cpufreq: kirkwood: Add a cpufreq driver for Marvell Kirkwood SoCsAndrew Lunn2013-02-091-0/+1
| | | | | | | | | | | The Marvell Kirkwood SoCs have simple cpufreq support in hardware. The CPU can either use the a high speed cpu clock, or the slower DDR clock. Add a driver to swap between these two clock sources. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 22:04:16 +0000