Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw) | Stephen Boyd | 2015-08-24 | 1 | -2/+2 |
* | clk: pistachio: Include clk.h | Stephen Boyd | 2015-07-20 | 1 | -0/+1 |
* | clk: pistachio: Add sanity checks on PLL configuration | Kevin Cernekee | 2015-06-04 | 1 | -4/+79 |
* | clk: pistachio: Lock the PLL when enabled upon rate change | Ezequiel Garcia | 2015-06-04 | 1 | -18/+10 |
* | clk: pistachio: Add a pll_lock() helper for clarity | Ezequiel Garcia | 2015-06-04 | 1 | -4/+8 |
* | CLK: Pistachio: Register external clock gates | Andrew Bresticker | 2015-03-31 | 1 | -0/+21 |
* | CLK: Pistachio: Register system interface gate clocks | Andrew Bresticker | 2015-03-31 | 1 | -0/+42 |
* | CLK: Pistachio: Register peripheral clocks | Andrew Bresticker | 2015-03-31 | 1 | -0/+67 |
* | CLK: Pistachio: Register core clocks | Andrew Bresticker | 2015-03-31 | 2 | -0/+200 |
* | CLK: Pistachio: Add PLL driver | Andrew Bresticker | 2015-03-31 | 3 | -0/+452 |
* | CLK: Add basic infrastructure for Pistachio clocks | Andrew Bresticker | 2015-03-31 | 3 | -0/+265 |