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* clk: qcom: Add GCC driver for SM8550Abel Vesa2022-12-011-0/+1
| | | | | | | | | | | | Add Global Clock controller (GCC) driver for SM8550 SoC, which includes the gcc resets and gdsc. This patch is based on an initial downstream driver. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-6-abel.vesa@linaro.org
* clk: qcom: Add display clock controller driver for SM6375Konrad Dybcio2022-11-151-0/+1
| | | | | | | | | Add support for the display clock controller found on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115155808.10899-2-konrad.dybcio@linaro.org
* clk: qcom: Add SC8280XP display clock controllerBjorn Andersson2022-11-091-0/+1
| | | | | | | | | | | | | | The Qualcomm SC8280XP platform has two display clock controller instances, add support for these. Duplication between the two implementations is reduced by reusing any constant data between the two sets of clock data. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926203800.16771-3-quic_bjorande@quicinc.com
* clk: qcom: Add global clock controller driver for SM6375Konrad Dybcio2022-09-271-0/+1
| | | | | | | | Add support for the global clock controller found on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921001303.56151-3-konrad.dybcio@somainline.org
* clk: qcom: Add SC8280XP GPU clock controllerBjorn Andersson2022-09-271-0/+1
| | | | | | | | | | | | Add driver for the GPU clock controller in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Included kernel.h and lower-cased hex numbers] Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926173025.4747-3-quic_bjorande@quicinc.com
* clk: qcom: Add support for Display Clock Controller on SM8450Dmitry Baryshkov2022-09-261-0/+1
| | | | | | | | Add support for the dispcc on Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-4-dmitry.baryshkov@linaro.org
* clk: qcom: Add display clock controller driver for SM6115Adam Skladowski2022-09-261-0/+1
| | | | | | | | | | | Add support for the display clock controller found in SM6115/SM4250 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based upon one submitted for QCM2290. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220911164635.182973-3-a39.skl@gmail.com
* clk: qcom: Add driver for MSM8909 GCCStephan Gerhold2022-09-131-0/+1
| | | | | | | | | | | | | | | | | | The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks, resets and power domains for the various hardware blocks in the SoC. Add a driver for it to make it possible to enable additional functionality for the SoC. Work on this driver was originally started independently by Dominik, I picked it up and added missing clocks/resets, as well as various cleanup to bring it into shape for mainline. Co-developed-by: Dominik Kobinski <dominikkobinski314@gmail.com> Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com> Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220706134132.3623415-3-stephan.gerhold@kernkonzept.com
* clk: qcom: add support for SM8350 GPUCCRobert Foss2022-07-061-0/+1
| | | | | | | | | | | The GPUCC manages the clocks for the Adreno GPU found on the sm8350 SoCs. Signed-off-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706154337.2026269-3-robert.foss@linaro.org
* clk: qcom: add camera clock controller driver for SM8450 SoCVladimir Zapolskiy2022-07-061-0/+1
| | | | | | | | | Add camera clock controller driver found on Qualcomm SM8450 SoC. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220701062744.2757931-1-vladimir.zapolskiy@linaro.org
* clk: qcom: regmap: add PHY clock source implementationDmitry Baryshkov2022-06-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On recent Qualcomm platforms the QMP PIPE clocks feed into a set of muxes which must be parked to the "safe" source (bi_tcxo) when corresponding GDSC is turned off and on again. Currently this is handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src clock. However the same code sequence should be applied in the pcie-qcom endpoint, USB3 and UFS drivers. Rather than copying this sequence over and over again, follow the example of clk_rcg2_shared_ops and implement this parking in the enable() and disable() clock operations. Supplement the regmap-mux with the new clk_regmap_phy_mux type, which implements such multiplexers as a simple gate clocks. This is possible since each of these multiplexers has just two clock sources: one coming from the PHY and a reference (XO) one. If the clock is running off the from-PHY source, report it as enabled. Report it as disabled otherwise (if it uses reference source). This way the PHY will disable the pipe clock before turning off the GDSC, which in turn would lead to disabling corresponding pipe_clk_src (and thus it being parked to a safe, reference clock source). And vice versa, after enabling the GDSC the PHY will enable the pipe clock, which would cause pipe_clk_src to be switched from a safe source to the working one. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220608105238.2973600-2-dmitry.baryshkov@linaro.org
* clk: qcom: add sc8280xp GCC driverBjorn Andersson2022-05-191-0/+1
| | | | | | | | | | Add support for the Global Clock Controller found in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org
* clk: qcom: lpass: Add support for LPASS clock controller for SC7280Taniya Das2022-04-121-0/+1
| | | | | | | | | | The Low Power Audio subsystem core and audio clocks are required for Audio client to be able to request for the clocks and power domains. Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220223172248.18877-2-tdas@codeaurora.org
* clk: qcom: Add display clock controller driver for SM6125Martin Botka2022-03-091-0/+1
| | | | | | | | | | | | Add support for the display clock controller found on SM6125 based devices. This allows display drivers to probe and control their clocks. Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303131812.302302-4-marijn.suijten@somainline.org
* clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and KconfigMarijn Suijten2022-03-091-1/+1
| | | | | | | | | | | | | In order to keep at least the list of `CONFIG_SM_` drivers sorted alphabetically, SDX_GCC_65 should have been moved one line up. This in turn makes it easier and cleaner to add the followup SM_DISPCC_6125 driver in the right place, right before SM_DISPCC_8250. Fixes: d79afa201328 ("clk: qcom: Add SDX65 GCC support") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303131812.302302-2-marijn.suijten@somainline.org
* clk: qcom: Add GPU clock controller driver for SM6350Konrad Dybcio2022-03-081-0/+1
| | | | | | | | Add support for the GPU clock controller found on SM6350. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-4-konrad.dybcio@somainline.org
* clk: qcom: Add display clock controller driver for SM6350Konrad Dybcio2022-03-081-0/+1
| | | | | | | | Add support for the display clock controller found on SM6350. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-2-konrad.dybcio@somainline.org
* clk: qcom: Add display clock controller driver for QCM2290Loic Poulain2022-02-101-0/+1
| | | | | | | | | | | | | | | | | | | Add support for the display clock controller found in QCM2290 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). It's a porting of dispcc-scuba GPL-2.0 driver from CAF msm-4.19 kernel: https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/drivers/clk/qcom/dispcc-scuba.c?h=LE.UM.4.4.1.r3 Global clock name references (parent_names) have been replaced by parent_data and parent_hws. Clocks marked enable_safe_config have their clk_rcg2_ops moved to clk_rcg2_shared_ops. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1644432308-21099-2-git-send-email-loic.poulain@linaro.org
* clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driverAngeloGioacchino Del Regno2021-12-161-0/+1
| | | | | | | | | | | | | | | | Add support for the global clock controller found on MSM8956 and MSM8976 SoCs. Since the multimedia clocks are actually in the GCC on these SoCs, this will allow drivers to probe and control basically all the required clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211208091036.132334-3-marijn.suijten@somainline.org
* clk: qcom: Add clock driver for SM8450Vinod Koul2021-12-161-0/+1
| | | | | | | | | | | | This adds Global Clock controller (GCC) driver for SM8450 SoC including the gcc resets and gdsc. This patch is based on initial code downstream by Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211207114003.100693-3-vkoul@kernel.org
* clk: qcom: Add SDX65 GCC supportVamsi Krishna Lanka2021-12-161-0/+1
| | | | | | | | | Add Global Clock Controller (GCC) support for SDX65 SoCs from Qualcomm. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/b5ea8a00d4e8418b57f4444d0b5243c1acc41808.1638861860.git.quic_vamslank@quicinc.com
* clk: qcom: camcc: Add camera clock controller driver for SC7280Taniya Das2021-10-131-0/+1
| | | | | | | | | | | Add support for the camera clock controller found on SC7280 based devices. This would allow camera drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633567425-11953-2-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Make some VCOs unsigned long] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add lpass clock controller driver for SC7280Taniya Das2021-10-131-0/+1
| | | | | | | | | | Add support for the lpass clock controller found on SC7280 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633484416-27852-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add Global Clock Controller driver for QCM2290Shawn Guo2021-10-131-0/+1
| | | | | | | | | | | | | | | Add Global Clock Controller (GCC) driver for QCM2290. This is a porting of gcc-scuba driver from CAF msm-4.19, with GDSC support added on top. Because the alpha_pll on the platform has a different register layout (offsets), its own clk_alpha_pll_regs_offset[] is used in the driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210919023308.24498-3-shawn.guo@linaro.org Acked-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Drop duplicate includes, clk.h include, module alias] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add SM6350 GCC driverKonrad Dybcio2021-08-291-0/+1
| | | | | | | | | This adds Global Clock controller (GCC) driver for SM6350 SoC Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210820203624.232268-3-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add Global Clock controller (GCC) driver for SM6115Iskren Chernev2021-08-281-0/+1
| | | | | | | | | | | | Add support for the global clock controller found on SM6115 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. GDSCs ported from downstream DT. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Link: https://lore.kernel.org/r/20210805161107.1194521-3-iskren.chernev@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add msm8994 MMCC driverKonrad Dybcio2021-08-261-0/+1
| | | | | | | | | | Add a driver for managing MultiMedia SubSystem clocks on msm8994 and its derivatives. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210618111435.595689-2-konrad.dybcio@somainline.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add Global Clock Controller driver for MSM8953Vladimir Lypak2021-08-261-0/+1
| | | | | | | | | | | | This driver provides clocks, resets and power domains for MSM8953 and compatible SoCs: APQ8053, SDM450, SDA450, SDM632, SDA632. Signed-off-by: Vladimir Lypak <junak.pub@gmail.com> Signed-off-by: Adam Skladowski <a_skl39@protonmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com> Link: https://lore.kernel.org/r/IPvVnyRWbHuQFswiFz0W08Kj1dKoH55ddQVyIIPhMJw@cp7-web-043.plabs.ch Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add video clock controller driver for SC7280Taniya Das2021-07-201-0/+1
| | | | | | | | | | Add support for the video clock controller found on SC7280 based devices. This would allow video drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1626189143-12957-8-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add graphics clock controller driver for SC7280Taniya Das2021-07-201-0/+1
| | | | | | | | | | Add support for the graphics clock controller found on SC7280 based devices. This would allow graphics drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1626189143-12957-6-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add display clock controller driver for SC7280Taniya Das2021-07-201-0/+1
| | | | | | | | | | Add support for the display clock controller found on SC7280 based devices. This would allow display drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1626189143-12957-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add camera clock controller driver for SM8250Jonathan Marek2021-06-271-0/+1
| | | | | | | | | | | | Add support for the camera clock controller found on SM8250. Based on the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20210609022051.2171-4-jonathan@marek.ca [sboyd@kernel.org: Add UL to avoid decimal problems] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add SM6125 (TRINKET) GCC driverKonrad Dybcio2021-06-271-0/+1
| | | | | | | | | | | | | Add the clocks supported in global clock controller, which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-2-martin.botka@somainline.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: Mark gcc_sm6125_hws array static] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add MDM9607 GCC driverKonrad Dybcio2021-06-021-0/+1
| | | | | | | | | Add Global Clock Controller (GCC) support for MDM9607 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210313020310.386152-2-konrad.dybcio@somainline.org [sboyd@kernel.org: Drop clk.h include] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add Global Clock controller (GCC) driver for SC7280Taniya Das2021-02-141-0/+1
| | | | | | | | | | Add support for the global clock controller found on SC7280 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1612981579-17391-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driverAngeloGioacchino Del Regno2021-02-141-0/+1
| | | | | | | | | The GPUCC manages the clocks for the Adreno GPU found on the SDM630, SDM636, SDM660 SoCs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-9-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driverMartin Botka2021-02-141-0/+1
| | | | | | | | | | | | | | | Add a driver for the multimedia clock controller found on SDM660 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Martin Botka <martin.botka@somainline.org> Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [angelogioacchino.delregno@somainline.org: Cleaned up SDM630 clock fixups] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-4-angelogioacchino.delregno@somainline.org [sboyd@kernel.org: Silence NULL pointer sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gcc: Add clock driver for SM8350Vivek Aknurwar2021-02-081-0/+1
| | | | | | | | | | | | This adds Global Clock controller (GCC) driver for SM8350 SoC Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210127070811.152690-6-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gcc: Add global clock controller driver for SC8180xBjorn Andersson2021-02-081-0/+1
| | | | | | | | | | Add clocks, resets and some of the GDSC provided by the global clock controller found in the Qualcomm SC8180x platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210126043155.1847823-2-bjorn.andersson@linaro.org [sboyd@kernel.org: Drop F macro as it's already defined] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add SDX55 APCS clock controller supportManivannan Sadhasivam2021-02-081-0/+1
| | | | | | | | | | | | | | | | | | | Add a driver for the SDX55 APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL This is required for enabling CPU frequency scaling on SDX55-based platforms. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118041156.50016-6-manivannan.sadhasivam@linaro.org [sboyd@kernel.org: Fix unused ret in probe by hardcoding it] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add A7 PLL supportManivannan Sadhasivam2021-02-081-0/+1
| | | | | | | | | | | | | | | Add support for PLL found in Qualcomm SDX55 platforms which is used to provide clock to the Cortex A7 CPU via a mux. This PLL can provide high frequency clock to the CPU above 1GHz as compared to the other sources like GPLL0. In this driver, the power domain is attached to the cpudev. This is required for CPUFreq functionality and there seems to be no better place to do other than this driver (no dedicated CPUFreq driver). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118041156.50016-5-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add SDX55 GCC supportNaveen Yadav2020-12-071-0/+1
| | | | | | | | | | | Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. Signed-off-by: Naveen Yadav <naveenky@codeaurora.org> [mani: converted to parent_data, commented critical clocks, cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20201126072844.35370-3-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocksSrinivas Kandagatla2020-11-041-0/+1
| | | | | | | | | GFM Muxes in AUDIO_CC control clocks to LPASS WSA and RX Codec Macros. This patch adds support to these muxes. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20201026120221.18984-4-srinivas.kandagatla@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: camcc: Add camera clock controller driver for SC7180Taniya Das2020-11-041-0/+1
| | | | | | | | | | Add support for the camera clock controller found on SC7180 based devices. This would allow camera drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1602873815-1677-5-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Mark hw array static, add UL to big vco numbers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add display clock controller driver for SM8150 and SM8250Jonathan Marek2020-10-131-0/+1
| | | | | | | | | Add support for the display clock controller found on SM8150 and SM8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: add video clock controller driver for SM8250Jonathan Marek2020-10-131-0/+1
| | | | | | | | | | Add support for the video clock controller found on SM8250 based devices. Derived from the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200923160635.28370-6-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: add video clock controller driver for SM8150Jonathan Marek2020-10-131-0/+1
| | | | | | | | | | Add support for the video clock controller found on SM8150 based devices. Derived from the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200923160635.28370-5-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: lpass: Add support for LPASS clock controller for SC7180Taniya Das2020-07-241-0/+1
| | | | | | | | | | The Low Power Audio subsystem clocks are required for Audio client to be able to request for the clocks and power domains. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-5-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Drop unused ret in probe function] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add graphics clock controller driver for SM8250Jonathan Marek2020-07-241-0/+1
| | | | | | | | | | | | | Add support for the graphics clock controller found on SM8250 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-12-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add graphics clock controller driver for SM8150Jonathan Marek2020-07-241-0/+1
| | | | | | | | | | | | | Add support for the graphics clock controller found on SM8150 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-11-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 02:53:56 +0000