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| | * clk: qcom: rpmh: Add support for RPMH clocks on SC7280Taniya Das2021-02-141-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | Add support for RPMH clocks on SC7280 SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1612977230-11566-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc-sm8350: add gdscVinod Koul2021-02-141-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | Add the GDSC found in GCC for SM8350 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210210161649.431741-1-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driverAngeloGioacchino Del Regno2021-02-143-0/+359
| | | | | | | | | | | | | | | | | | | | | | | | | | | The GPUCC manages the clocks for the Adreno GPU found on the SDM630, SDM636, SDM660 SoCs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-9-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3dAngeloGioacchino Del Regno2021-02-141-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the previous commit ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops) were generalized in order to be able to reuse the same ops for more than just one clock for one SoC: follow the change here in the MSM8996 MMCC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-7-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbersAngeloGioacchino Del Regno2021-02-142-20/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function clk_gfx3d_determine_rate is selecting different PLLs to manage the GFX3D clock source in a special way: this one needs to be ping-pong'ed on different PLLs to ensure stability during frequency switching (set a PLL rate, let it stabilize, switch the RCG to the new PLL) and fast frequency transitions. This technique is currently being used in the MSM8996 SoC and the function was assuming that the parents were always at a specific index in the parents list, which is TRUE, if we use this only on the MSM8996 MMCC. Unfortunately, MSM8996 is not the only SoC that needs to ping-pong the graphics RCG, so choices are: 1. Make new special ops just to hardcode *again* other indexes, creating code duplication for (imo) no reason; or 2. Generalize this function, so that it becomes usable for a range of SoCs with slightly different ping-pong configuration. In this commit, the second road was taken: define a new "special" struct clk_rcg2_gfx3d, containing the ordered list of parents to ping-pong the graphics clock on, and the "regular" rcg2 clock structure in order to generalize the clk_gfx3d_determine_rate function and make it working for other SoCs. As for the function itself it is left with the assumption that we need to ping-pong over three parents. The reasons for this are: 1. The initial model was MSM8996, which has 3 parents for the graphics clock pingpong; 2. The other example that was taken into consideration is the SDM630/636/660 SoC gpu clock controller, which is ping-ponging over two dynamic clocked and one fixed clock PLL. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-6-angelogioacchino.delregno@somainline.org [sboyd@kernel.org: Grow some local variables, drop do_div() usage in favor of plain division, we're not dealing with a u64 here] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driverMartin Botka2021-02-143-0/+2874
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the multimedia clock controller found on SDM660 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Martin Botka <martin.botka@somainline.org> Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [angelogioacchino.delregno@somainline.org: Cleaned up SDM630 clock fixups] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-4-angelogioacchino.delregno@somainline.org [sboyd@kernel.org: Silence NULL pointer sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as criticalAngeloGioacchino Del Regno2021-02-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is critical for any access to the GPU: gating it will crash the system when the GPU has been initialized (so, you cannot gate it unless you deinit the Adreno completely). So, to achieve a working state with GPU on, set the CLK_IS_CRITICAL flag to this clock. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-3-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as criticalAngeloGioacchino Del Regno2021-02-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Similarly to MSM8998, any access to the MMSS depends on this clock. Gating it will crash the system when RPMCC inits mmssnoc_axi_rpm_clk. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-2-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate settingAngeloGioacchino Del Regno2021-02-141-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPU PLL0 is not a fixed PLL and the rate can be set on it: this is necessary especially on boards which bootloader is setting a very low rate on this PLL before booting Linux, which would be unsuitable for postdividing to reach the maximum allowed Adreno GPU frequency of 710MHz (or, actually, even 670MHz..) on this SoC. To allow setting rates on the GPU PLL0, also define VCO boundaries and set the CLK_SET_RATE_PARENT flag to the GPU PLL0 postdivider. With this change, the Adreno GPU is now able to scale through all the available frequencies. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-12-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdscAngeloGioacchino Del Regno2021-02-141-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPU GX GDSC has GPU_GX_BCR reset and gfx3d_clk CXC, as stated on downstream kernels (and as verified upstream, because otherwise random lockups happen). Also, add PWRSTS_RET and NO_RET_PERIPH: also as found downstream, and also as verified here, to avoid GPU related lockups it is necessary to force retain mem, but *not* peripheral when enabling this GDSC (and, of course, the inverse on disablement). With this change, the GPU finally works flawlessly on my four different MSM8998 devices from two different manufacturers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-11-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gdsc: Implement NO_RET_PERIPH flagAngeloGioacchino Del Regno2021-02-142-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some rare occasions, we want to only set the RETAIN_MEM bit, but not the RETAIN_PERIPH one: this is seen on at least SDM630/636/660's GPU-GX GDSC, where unsetting and setting back the RETAIN_PERIPH bit will generate chaos and panics during GPU suspend time (mainly, the chaos is unaligned access). For this reason, introduce a new NO_RET_PERIPH flag to the GDSC driver to address this corner case. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-8-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always onAngeloGioacchino Del Regno2021-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This GDSC enables (or cuts!) power to the Multimedia Subsystem IOMMU (mmss smmu), which has bootloader pre-set secure contexts. In the event of a complete power loss, the secure contexts will be reset and the hypervisor will crash the SoC. To prevent this, and get a working multimedia subsystem, set this GDSC as always on. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-10-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clksAngeloGioacchino Del Regno2021-02-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware clock gating is supported on some of the clocks declared in there: ignoring that it does exist may lead to unstabilities on some firmwares. Add the HWCG registers where applicable to stop potential crashes. This was verified on a smartphone shipped with a recent MSM8998 firmware, which will experience random crashes without this change. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-9-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno2021-02-081-50/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs and not generic alphas: this was producing bad effects over the entire clock tree of MSM8998, where any GPLL child clock was declaring a false clock rate, due to their parent also showing the same. The issue resides in the calculation of the clock rate for the specific Alpha PLL type, where Fabia has a different register layout; switching the MSM8998 GPLLs to the correct Alpha Fabia PLL type fixes the rate (calculation) reading. While at it, also make these PLLs fixed since their rate is supposed to *never* be changed while the system runs, as this would surely crash the entire SoC. Now all the children of all the PLLs are also complying with their specified clock table and system stability is improved. Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-7-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as criticalAngeloGioacchino Del Regno2021-02-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPU IOMMU depends on this clock and the hypervisor will crash the SoC if this clock gets disabled because the secure contexts that have been set on this IOMMU by the bootloader will become unaccessible (or they get reset). Mark this clock as critical to avoid this issue when the Adreno GPU is enabled. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-6-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clockAngeloGioacchino Del Regno2021-02-081-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | To achieve CPR-Hardened functionality this clock must be on: add it in order to be able to get it managed by the CPR3 driver. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-5-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clockAngeloGioacchino Del Regno2021-02-081-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | This clock enables the GPLL0 output to the multimedia subsystem clock controller. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-3-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: videocc: Add gdsc mmcx-reg supply hookBryan O'Donoghue2021-02-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a regulator supply hook to mmcx-reg missing from - mvs0c_gdsc - mvs1c_gdsc - mvs0_gdsc - mvs1_gdsc Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210204150120.1521959-5-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: videocc: Add sm8250 VIDEO_CC_MVS0_CLKBryan O'Donoghue2021-02-081-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the missing video_cc_mvs0_clk entry to videocc-sm8250 replicating in upstream the explicit entry for this clock in downstream. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210204150120.1521959-4-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: videocc: Add sm8250 VIDEO_CC_MVS0_DIV_CLK_SRCBryan O'Donoghue2021-02-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the missing video_cc_mvs0_div_clk_src entry to videocc-sm8250 replicating in upstream the explicit entry for this clock in downstream. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210204150120.1521959-3-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc: Add clock driver for SM8350Vivek Aknurwar2021-02-083-0/+3799
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds Global Clock controller (GCC) driver for SM8350 SoC Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210127070811.152690-6-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLLVivek Aknurwar2021-02-082-0/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lucid 5LPE is a slightly different Lucid PLL with different offsets and porgramming sequence so add support for these Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210127070811.152690-4-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate()Vinod Koul2021-02-081-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but with different registers. Modularize these by moving out latch and latch ack bits so that we can reuse the function. Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210127070811.152690-3-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: clk-alpha-pll: replace regval with valVinod Koul2021-02-081-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver uses regval variable for holding register values, replace with a shorter one val Suggested-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210127070811.152690-2-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc: Add global clock controller driver for SC8180xBjorn Andersson2021-02-083-0/+4639
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clocks, resets and some of the GDSC provided by the global clock controller found in the Qualcomm SC8180x platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210126043155.1847823-2-bjorn.andersson@linaro.org [sboyd@kernel.org: Drop F macro as it's already defined] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gcc-sc7180: Mark the MM XO clocks to be always ONTaniya Das2021-02-081-43/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are intermittent GDSC power-up failures observed for titan top gdsc, which requires the XO clock. Thus mark all the MM XO clocks always enabled from probe. Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1611128871-5898-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: rpmhcc: Add sc8180x rpmh clocksBjorn Andersson2021-02-081-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Add clocks provides by RPMH in the Qualcomm SC8180x platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210120223741.1610344-2-bjorn.andersson@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: gfm-mux: fix clk maskSrinivas Kandagatla2021-02-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason global GFM_MASK ended up with bit 1 instead of bit 0. Remove the global GFM_MASK and reuse mux_mask field. Fixes: a2d8f507803e ("clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210119113851.18946-1-srinivas.kandagatla@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: Add SDX55 APCS clock controller supportManivannan Sadhasivam2021-02-083-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the SDX55 APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL This is required for enabling CPU frequency scaling on SDX55-based platforms. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118041156.50016-6-manivannan.sadhasivam@linaro.org [sboyd@kernel.org: Fix unused ret in probe by hardcoding it] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: qcom: Add A7 PLL supportManivannan Sadhasivam2021-02-083-0/+109
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for PLL found in Qualcomm SDX55 platforms which is used to provide clock to the Cortex A7 CPU via a mux. This PLL can provide high frequency clock to the CPU above 1GHz as compared to the other sources like GPLL0. In this driver, the power domain is attached to the cpudev. This is required for CPUFreq functionality and there seems to be no better place to do other than this driver (no dedicated CPUFreq driver). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118041156.50016-5-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gcc-sm250: Use floor ops for sdcc clksDmitry Baryshkov2021-01-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | Followup to the commits 5e4b7e82d497 ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") and 6d37a8d19283 ("clk: qcom: gcc-sc7180: Use floor ops for sdcc clks"). Use floor ops for sdcc clocks on sm8250. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Link: https://lore.kernel.org/r/20210109013314.3443134-1-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gcc-sc7180: Mark the camera abh clock always ONTaniya Das2021-01-121-18/+3
|/ | | | | | | | | | | | The camera clock controller requires the AHB clock, the driver when moved to use the pm_runtime_get() API, the camera ahb clock failed turn on before access, thus mark it as always ON. Reported-by: Stephen Boyd <sboyd@kernel.org> Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1608573816-1465-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2020-12-2111-138/+4019
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework got some nice improvements this time around. We gained the ability to get struct clk pointers from a struct clk_hw so that clk providers can consume the clks they provide, if they need to do something like that. This has been a long missing part of the clk provider API that will help us move away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are added for the clk_set_rate() "range" functions, similar to the tracepoints we already have for clk_set_rate() and we added a column to debugfs to help developers understand the hardware enable state of clks in case firmware or bootloader state is different than what is expected. Overall the core changes are mostly improving the clk driver writing experience. At the driver level, we have the usual collection of driver updates and new drivers for new SoCs. This time around the Qualcomm folks introduced a good handful of clk drivers for various parts of three or four SoCs. The SiFive folks added a new clk driver for their FU740 SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that for various new features. One last thing to note in the driver area is that the i.MX driver has gained a new binding to support SCU clks after being on the list for many months. It uses a two cell binding which is sort of rare in clk DT bindings. Beyond that we have the usual set of driver fixes and tweaks that come from more testing and finding out that some configuration was wrong or that a driver could support being built as a module. Summary: Core: - Add some trace points for clk_set_rate() "range" functions - Add hardware enable information to clk_summary debugfs - Replace clk-provider.h with of_clk.h when possible - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw New Drivers: - Bindings for Canaan K210 SoC clks - Support for SiFive FU740 PRCI - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs Updates: - DVFS support for AT91 clk driver - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors in Renesas clk drivers - One more conversion of DT bindings to json-schema - Make i.MX clk-gate2 driver more flexible - New two cell binding for i.MX SCU clks - Drop of_match_ptr() in i.MX8 clk drivers - Add arch dependencies for Rockchip clk drivers - Fix i2s on Rockchip rk3066 - Add MIPI DSI clks on Amlogic axg and g12 SoCs - Support modular builds of Amlogic clk drivers - Fix an Amlogic Video PLL clock dependency - Samsung Kconfig dependencies updates for better compile test coverage - Refactoring of the Samsung PLL clocks driver - Small Tegra driver cleanups - Minor fixes to Ingenic and VC5 clk drivers - Cleanup patches to remove unused variables and plug memory leaks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" clk: ingenic: Fix divider calculation with div tables clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 clk: si5351: Wait for bit clear after PLL reset clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error ...
| * clk: qcom: rpmh: add support for SM8350 rpmh clocksVinod Koul2020-12-101-12/+46
| | | | | | | | | | | | | | | | | | | | This adds the RPMH clocks present in SM8350 SoC Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20201208064702.3654324-3-vkoul@kernel.org [sboyd@kernel.org: Move sdx55 to the right place] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: lpasscc: Introduce pm autosuspend for SC7180Taniya Das2020-12-101-1/+9
| | | | | | | | | | | | | | | | | | The LPASSCC driver's suspend/resume is invoked multiple number of times and thus allow the device to autosuspend for 500ms. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1605890417-721-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2Douglas Anderson2020-12-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 50 MHz is an incredibly common clock rate for SD cards to run at. It's "high speed" mode in SD (not very fast these days, but it used to be) or: #define HIGH_SPEED_MAX_DTR 50000000 If we don't support this then older "high speed" cards can only run at 25 MHz or at half their normal speed. There doesn't seem to be any reason to skip this clock rate, so add it. Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201210102234.2.I26dcc0cee374f5571d9929c9985f463773167e68@changeid Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc-sc7180: Use floor ops for sdcc clksDouglas Anderson2020-12-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I would repeat the same commit message that was in commit 5e4b7e82d497 ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems silly to do so when you could just go read that commit. NOTE: this is actually extra terrible because we're missing the 50 MHz rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2")). That means then when you run an older SD card it'll try to clock it at 100 MHz when it's only specced to run at 50 MHz max. As you can probably guess that doesn't work super well. Signed-off-by: Douglas Anderson <dianders@chromium.org> Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Link: https://lore.kernel.org/r/20201210102234.1.I096779f219625148900fc984dd0084ed1ba87c7f@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: Add GDSC support for SDX55 GCCManivannan Sadhasivam2020-12-072-0/+34
| | | | | | | | | | | | | | | | | | Add GDSC support to control the power supply of power domains in SDX55 GCC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201126072844.35370-7-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: Add support for SDX55 RPMh clocksManivannan Sadhasivam2020-12-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for following clocks maintained by RPMh in SDX55 SoCs. * BI TCXO * RF_CLK1 * RF_CLK1_AO * RF_CLK2 * RF_CLK2_AO * QPIC (Qualcomm Technologies, Inc. Parallel Interface Controller) Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201126072844.35370-5-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: Add SDX55 GCC supportNaveen Yadav2020-12-073-0/+1634
| | | | | | | | | | | | | | | | | | | | | | Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. Signed-off-by: Naveen Yadav <naveenky@codeaurora.org> [mani: converted to parent_data, commented critical clocks, cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20201126072844.35370-3-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"Colin Ian King2020-11-271-1/+1
| | | | | | | | | | | | | | | | There is a spelling mistake in the Kconfig help text. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20201126232400.15011-1-colin.king@canonical.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: rpmh: Add CE clock on sdm845.Thara Gopinath2020-11-241-0/+2
| | | | | | | | | | | | | | | | | | | | Qualcomm CE clock resource that is managed by BCM is required by crypto driver to access the core clock. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Link: https://lore.kernel.org/r/20201119155233.3974286-3-thara.gopinath@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: dispcc-sm8250: handle MMCX power domainDmitry Baryshkov2020-11-141-0/+1
| | | | | | | | | | | | | | | | | | | | On SM8250 MMCX power domain is required to access MMDS_GDSC registers. This power domain is expressed as mmcx-supply regulator property. Use this regulator as MDSS_GDSC supply. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20201023131925.334864-6-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk onesStephen Boyd2020-11-141-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's call pm_runtime_get() here instead of calling the PM clk APIs directly. This avoids a compilation problem on CONFIG_PM=n where the pm_clk_runtime_{resume,suspend}() functions don't exist and covers the intent, i.e. enable the clks for this device so we can program PLL settings. Reported-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Nathan Chancellor <natechancellor@gmail.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Taniya Das <tdas@codeaurora.org> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for SC7180") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201114174408.579047-1-sboyd@kernel.org
| * clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()Dan Carpenter2020-11-141-1/+7
| | | | | | | | | | | | | | | | | | | | Clean up the first driver if the second driver can't be registered. Fixes: 4ee9fe3e292b ("clk: qcom: lpass-sc7180: Disentangle the two clock devices") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20201113101419.GC168908@mwanda Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocksSrinivas Kandagatla2020-11-041-0/+63
| | | | | | | | | | | | | | | | | | | | LPASS Always ON Clock controller has one GFM mux to control VA and TX clocks to codec macro on LPASS. This patch adds support to this mux. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20201026120221.18984-5-srinivas.kandagatla@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocksSrinivas Kandagatla2020-11-043-0/+264
| | | | | | | | | | | | | | | | | | GFM Muxes in AUDIO_CC control clocks to LPASS WSA and RX Codec Macros. This patch adds support to these muxes. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20201026120221.18984-4-srinivas.kandagatla@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: lpass-sc7180: Disentangle the two clock devicesDouglas Anderson2020-11-041-39/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | The sc7180 lpass clock driver manages two different devices. These two devices were tangled together, using one probe and a lookup to figure out the real probe. I think it's cleaner to really separate the probe for these two devices since they're really different things, just both managed by the same driver. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201019154857.v5.2.I75c409497d4dea9daefa53ec5f93824081c4ecbe@changeid Reviewed-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: lpasscc-sc7810: Use devm in probeDouglas Anderson2020-11-041-17/+21
| | | | | | | | | | | | | | | | | | | | Let's convert the lpass clock control driver to use devm. This is a few more lines of code, but it will be useful in a later patch which disentangles the two devices handled by this driver. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201019154857.v5.1.I4567b5e7e17bbb15ef063d447cb83fd43746cb18@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: camcc: Add camera clock controller driver for SC7180Taniya Das2020-11-043-0/+1746
| | | | | | | | | | | | | | | | | | | | Add support for the camera clock controller found on SC7180 based devices. This would allow camera drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1602873815-1677-5-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Mark hw array static, add UL to big vco numbers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-11 04:06:55 +0000