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| | * clk: qcom: gcc-sm6125: Remove gpll7 from sdcc2_appsMartin Botka2022-11-051-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This removes gpll7 clock source from sdcc2_apps as it caused issues on the device during testing Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221001185431.493440-1-martin.botka@somainline.org
| | * clk: qcom: gcc-ipq806x: use parent_data for the last remaining entryDmitry Baryshkov2022-11-051-1/+3
| |/ | | | | | | | | | | | | | | | | | | | | Use parent_data for the last remaining entry (pll4). This clock is provided by the lcc device. Fixes: cb02866f9a74 ("clk: qcom: gcc-ipq806x: convert parent_names to parent_data") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927113826.246241-3-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-sc8280xp: add cxo as parent for three ufs ref clksShazad Hussain2022-11-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The three UFS reference clocks, gcc_ufs_ref_clkref_clk for external UFS devices, gcc_ufs_card_clkref_clk and gcc_ufs_1_card_clkref_clk for two PHYs are all sourced from CXO. Added parent_data for all three reference clocks described above to reflect that all three clocks are sourced from CXO to have valid frequency for the ref clock needed by UFS controller driver. Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") Link: https://lore.kernel.org/lkml/Y2Tber39cHuOSR%2FW@hovoldconsulting.com/ Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/20221115152956.21677-1-quic_shazhuss@quicinc.com Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gdsc: Remove direct runtime PM callsStephen Boyd2022-11-042-57/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We shouldn't be calling runtime PM APIs from within the genpd enable/disable path for a couple reasons. First, this causes an AA lockdep splat[1] because genpd can call into genpd code again while holding the genpd lock. WARNING: possible recursive locking detected 5.19.0-rc2-lockdep+ #7 Not tainted -------------------------------------------- kworker/2:1/49 is trying to acquire lock: ffffffeea0370788 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30 but task is already holding lock: ffffffeea03710a8 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&genpd->mlock); lock(&genpd->mlock); *** DEADLOCK *** May be due to missing lock nesting notation 3 locks held by kworker/2:1/49: #0: 74ffff80811a5748 ((wq_completion)pm){+.+.}-{0:0}, at: process_one_work+0x320/0x5fc #1: ffffffc008537cf8 ((work_completion)(&genpd->power_off_work)){+.+.}-{0:0}, at: process_one_work+0x354/0x5fc #2: ffffffeea03710a8 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x24/0x30 stack backtrace: CPU: 2 PID: 49 Comm: kworker/2:1 Not tainted 5.19.0-rc2-lockdep+ #7 Hardware name: Google Lazor (rev3 - 8) with KB Backlight (DT) Workqueue: pm genpd_power_off_work_fn Call trace: dump_backtrace+0x1a0/0x200 show_stack+0x24/0x30 dump_stack_lvl+0x7c/0xa0 dump_stack+0x18/0x44 __lock_acquire+0xb38/0x3634 lock_acquire+0x180/0x2d4 __mutex_lock_common+0x118/0xe30 mutex_lock_nested+0x70/0x7c genpd_lock_mtx+0x24/0x30 genpd_runtime_suspend+0x2f0/0x414 __rpm_callback+0xdc/0x1b8 rpm_callback+0x4c/0xcc rpm_suspend+0x21c/0x5f0 rpm_idle+0x17c/0x1e0 __pm_runtime_idle+0x78/0xcc gdsc_disable+0x24c/0x26c _genpd_power_off+0xd4/0x1c4 genpd_power_off+0x2d8/0x41c genpd_power_off_work_fn+0x60/0x94 process_one_work+0x398/0x5fc worker_thread+0x42c/0x6c4 kthread+0x194/0x1b4 ret_from_fork+0x10/0x20 Second, this confuses runtime PM on CoachZ for the camera devices by causing the camera clock controller's runtime PM usage_count to go negative after resuming from suspend. This is because runtime PM is being used on the clock controller while runtime PM is disabled for the device. The reason for the negative count is because a GDSC is represented as a genpd and each genpd that is attached to a device is resumed during the noirq phase of system wide suspend/resume (see the noirq suspend ops assignment in pm_genpd_init() for more details). The camera GDSCs are attached to camera devices with the 'power-domains' property in DT. Every device has runtime PM disabled in the late system suspend phase via __device_suspend_late(). Runtime PM is not usable until runtime PM is enabled in device_resume_early(). The noirq phases run after the 'late' and before the 'early' phase of suspend/resume. When the genpds are resumed in genpd_resume_noirq(), we call down into gdsc_enable() that calls pm_runtime_resume_and_get() and that returns -EACCES to indicate failure to resume because runtime PM is disabled for all devices. Upon closer inspection, calling runtime PM APIs like this in the GDSC driver doesn't make sense. It was intended to make sure the GDSC for the clock controller providing other GDSCs was enabled, specifically the MMCX GDSC for the display clk controller on SM8250 (sm8250-dispcc), so that GDSC register accesses succeeded. That will already happen because we make the 'dev->pm_domain' a parent domain of each GDSC we register in gdsc_register() via pm_genpd_add_subdomain(). When any of these GDSCs are accessed, we'll enable the parent domain (in this specific case MMCX). We also remove any getting of runtime PM during registration, because when a genpd is registered it increments the count on the parent if the genpd itself is already enabled. Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Johan Hovold <johan+linaro@kernel.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Taniya Das <quic_tdas@quicinc.com> Cc: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Reported-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/CAE-0n52xbZeJ66RaKwggeRB57fUAwjvxGxfFMKOKJMKVyFTe+w@mail.gmail.com [1] Fixes: 1b771839de05 ("clk: qcom: gdsc: enable optional power domain support") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20221103183030.3594899-1-swboyd@chromium.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: Update the force mem core bit for GPU clocksTaniya Das2022-10-272-0/+2
|/ | | | | | | | | | | | | | There are few GPU clocks which are powering up the memories and thus enable the FORCE_MEM_PERIPH always for these clocks to force the periph_on signal to remain active during halt state of the clock. Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Fixes: 3e0f01d6c7e7 ("clk: qcom: Add graphics clock controller driver for SC7280") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Link: https://lore.kernel.org/r/1666159535-6447-1-git-send-email-quic_c_skakit@quicinc.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge branch 'clk-rate-range' into clk-nextStephen Boyd2022-10-141-0/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Various clk rate range fixes - Drop clk rate range constraints on clk_put() (redux) * clk-rate-range: (28 commits) clk: mediatek: clk-mux: Add .determine_rate() callback clk: tests: Add tests for notifiers clk: Update req_rate on __clk_recalc_rates() clk: tests: Add missing test case for ranges clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d clk: Introduce the clk_hw_get_rate_range function clk: Zero the clk_rate_request structure clk: Stop forwarding clk_rate_requests to the parent clk: Constify clk_has_parent() clk: Introduce clk_core_has_parent() clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock clk: Add our request boundaries in clk_core_init_rate_req clk: Introduce clk_hw_init_rate_request() clk: Move clk_core_init_rate_req() from clk_core_round_rate_nolock() to its caller clk: Change clk_core_init_rate_req prototype clk: Set req_rate on reparenting clk: Take into account uncached clocks in clk_set_rate_range() clk: tests: Add some tests for orphan with multiple parents clk: tests: Add tests for mux with multiple parents clk: tests: Add tests for single parent mux ...
| * clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3dMaxime Ripard2022-09-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gfx3d clock is hand-crafting its own clk_rate_request in clk_gfx3d_determine_rate to pass to the parent of that clock. However, since the clk_rate_request is zero'd at creation, it will have a max_rate of 0 which will break any code depending on the clock boundaries. That includes the recent commit 948fb0969eae ("clk: Always clamp the rounded rate") which will clamp the rate given to clk_round_rate() to the current clock boundaries. For the gfx3d clock, it means that since both the min_rate and max_rate fields are set at zero, clk_round_rate() now always return 0. Let's initialize the min_rate and max_rate fields properly for that clock. Fixes: 948fb0969eae ("clk: Always clamp the rounded rate") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220816112530.1837489-25-maxime@cerno.tech Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gcc-msm8660: Drop hardcoded fixed board clocksLinus Walleij2022-10-141-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These two clocks are now registered in the device tree as fixed clocks, causing a regression in the driver as the clock already exists with e.g. the name "pxo_board" as the MSM8660 GCC driver probes. Fix this by just not hard-coding this anymore and everything works like a charm. Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: baecbda52933 ("ARM: dts: qcom: msm8660: fix node names for fixed clocks") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20221013140745.7801-1-linus.walleij@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gcc-sm6375: Ensure unsigned long typeStephen Boyd2022-10-041-1/+1
| | | | | | | | | | | | | | | | | | This PLL frequency needs a UL postfix to avoid compiler warnings on 32-bit architectures. Fixes: 184fdd873d83 ("clk: qcom: Add global clock controller driver for SM6375") Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gcc-sm6375: Remove unused variablesKonrad Dybcio2022-10-041-12/+0
| | | | | | | | | | | | | | | | | | | | gcc_parent_data_15 and gcc_parent_map_15 are not used in this driver. Remove them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20221003211438.25691-1-konrad.dybcio@somainline.org Fixes: 184fdd873d83 ("clk: qcom: Add global clock controller driver for SM6375") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: kpss-xcc: convert to parent data APIChristian Marangi2022-10-031-17/+9
| | | | | | | | | | | | | | | | | | | | | | | | Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. .name is changed to the legacy pxo_board following how it's declared in other drivers. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220914144743.17369-2-ansuelsmth@gmail.com Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov2022-09-291-60/+60
| | | | | | | | | | | | | | | | | | | | Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928145609.375860-4-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-msm8939: use parent_hws where possibleDmitry Baryshkov2022-09-291-216/+216
| | | | | | | | | | | | | | | | | | Use parent_hws instead of hanving parent_data with just a single .hw entry to speed up and simplify parent lookups. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928145609.375860-3-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscsLuca Weiss2022-09-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB controllers on sm6350 do not retain the state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Fix this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928132853.179425-1-luca.weiss@fairphone.com
* | clk: qcom: gcc-sc8280xp: use retention for USB power domainsJohan Hovold2022-09-291-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Since commit d399723950c4 ("clk: qcom: gdsc: Fix the handling of PWRSTS_RET support) retention mode can be used on sc8280xp to maintain state during suspend instead of leaving the domain always on. This is needed to eventually allow the parent CX domain to be powered down during suspend. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220929161124.18138-1-johan+linaro@kernel.org
* | clk: qcom: gdsc: add missing error handlingJohan Hovold2022-09-291-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 7eb231c337e0 ("PM / Domains: Convert pm_genpd_init() to return an error code") pm_genpd_init() can return an error which the caller must handle. The current error handling was also incomplete as the runtime PM and regulator use counts were not balanced in all error paths. Add the missing error handling to the GDSC initialisation to avoid continuing as if nothing happened on errors. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220929155816.17425-1-johan+linaro@kernel.org
* | clk: qcom: Add global clock controller driver for SM6375Konrad Dybcio2022-09-273-0/+3940
| | | | | | | | | | | | | | | | Add support for the global clock controller found on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921001303.56151-3-konrad.dybcio@somainline.org
* | clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bitKonrad Dybcio2022-09-272-2/+8
| | | | | | | | | | | | | | | | This is used on at least SM6375 and its variations. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921001303.56151-1-konrad.dybcio@somainline.org
* | clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscsRajendra Nayak2022-09-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB controllers on sc7280 do not retain the state when the system goes into low power state and the GDSCs are turned off. This results in the controllers reinitializing and re-enumerating all the connected devices (resulting in additional delay while coming out of suspend) Fix this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. Since sc7280 only supports cx (parent of usb gdscs) Retention, there are no cxcs offsets mentioned in order to support the Retention state. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920111517.10407-3-quic_rjendra@quicinc.com
* | clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdscRajendra Nayak2022-09-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB controller on sc7180 does not retain the state when the system goes into low power state and the GDSC is turned off. This results in the controller reinitializing and re-enumerating all the connected devices (resulting in additional delay while coming out of suspend) Fix this by updating the .pwrsts for the USB GDSC so it only transitions to retention state in low power. Since sc7180 only supports cx (parent of usb gdsc) Retention, there are no cxcs offsets mentioned in order to support the Retention state. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920111517.10407-2-quic_rjendra@quicinc.com
* | clk: qcom: gdsc: Fix the handling of PWRSTS_RET supportRajendra Nayak2022-09-272-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GDSCs cannot be transitioned into a Retention state in SW. When either the RETAIN_MEM bit, or both the RETAIN_MEM and RETAIN_PERIPH bits are set, and the GDSC is left ON, the HW takes care of retaining the memory/logic for the domain when the parent domain transitions to power collapse/power off state. On some platforms where the parent domains lowest power state itself is Retention, just leaving the GDSC in ON (without any RETAIN_MEM/RETAIN_PERIPH bits being set) will also transition it to Retention. The existing logic handling the PWRSTS_RET seems to set the RETAIN_MEM/RETAIN_PERIPH bits if the cxcs offsets are specified but then explicitly turns the GDSC OFF as part of _gdsc_disable(). Fix that by leaving the GDSC in ON state. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920111517.10407-1-quic_rjendra@quicinc.com
* | clk: qcom: Add SC8280XP GPU clock controllerBjorn Andersson2022-09-273-0/+470
| | | | | | | | | | | | | | | | | | | | | | | | Add driver for the GPU clock controller in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Included kernel.h and lower-cased hex numbers] Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926173025.4747-3-quic_bjorande@quicinc.com
* | clk: qcom: smd: Add SM6375 clocksKonrad Dybcio2022-09-271-2/+44
| | | | | | | | | | | | | | | | Add support for controlling SMD RPM clocks on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921004458.151842-3-konrad.dybcio@somainline.org
* | clk: qcom: rpmhcc: add sdm670 clocksRichard Acayan2022-09-271-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | The Snapdragon 670 uses the RPMh mailbox for most of the clocks used in SDM845 but omits two. Add clock data for SDM670 so the driver doesn't fail to resolve a clock. Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F7 Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920223734.151135-3-mailingradian@gmail.com
* | clk: qcom: Merge alt alpha plls for qcm2260, sm6115Iskren Chernev2022-09-264-82/+57
| | | | | | | | | | | | | | | | | | | | | | The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and BRAMMO alpha pll offsets. Move these common offsets to the shared place to avoid duplication. The new layouts have a suffix EVO similar to LUCID and RIVIAN. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830075620.974009-4-iskren.chernev@gmail.com
* | clk: qcom: gcc-sm6115: Move alpha pll bramo overridesIskren Chernev2022-09-261-14/+12
| | | | | | | | | | | | | | | | | | sm6115 uses a modified default and bramo alpha pll offsets. Put them in the same place for consistency. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830075620.974009-3-iskren.chernev@gmail.com
* | clk: qcom: gcc-sm6115: Override default Alpha PLL regsAdam Skladowski2022-09-261-16/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but currently only BRAMMO ones are overridden. Override DEFAULT ones too. A very similar thing is happening in gcc-qcm2290 driver. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Adam Skladowski <a_skl39@protonmail.com> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830075620.974009-2-iskren.chernev@gmail.com
* | clk: qcom: Add support for Display Clock Controller on SM8450Dmitry Baryshkov2022-09-263-0/+1839
| | | | | | | | | | | | | | | | Add support for the dispcc on Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-4-dmitry.baryshkov@linaro.org
* | clk: qcom: alpha-pll: add support for power off mode for lucid evo PLLDmitry Baryshkov2022-09-262-3/+38
| | | | | | | | | | | | | | | | | | | | PLLs can be kept in standby (default configuration) or in off mode when disabled during power collapse. Hence add support for pll disable off mode for lucid evo PLL. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-3-dmitry.baryshkov@linaro.org
* | clk: qcom: Add display clock controller driver for SM6115Adam Skladowski2022-09-263-0/+618
| | | | | | | | | | | | | | | | | | | | | | Add support for the display clock controller found in SM6115/SM4250 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based upon one submitted for QCM2290. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220911164635.182973-3-a39.skl@gmail.com
* | clk: qcom: gcc-sc7280: Update the .pwrsts for PCIe GDSCKrishna chaitanya chundru2022-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | Enabling PCIe GDSC retention to ensure controller and its dependent clocks won't go down during system suspend. Update the .pwrsts for PCIe GDSC so it only transitions to RET in low power. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1663669347-29308-6-git-send-email-quic_krichai@quicinc.com
* | clk: qcom: lpass: Fix lpass audiocc probeSatya Priya2022-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Change the qcom_cc_probe_by_index() call to qcom_cc_really_probe() to avoid remapping of memory region for index 0, which is already being done through qcom_cc_map(). Fixes: 7c6a6641c2 ("clk: qcom: lpass: Add support for resets & external mclk for SC7280") Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@baylibre.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1663673683-7018-1-git-send-email-quic_c_skakit@quicinc.com
* | clk: qcom: apss-ipq-pll: add support for IPQ8074Robert Marko2022-09-261-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add support for IPQ8074 since it uses the same PLL setup, however it uses slightly different Alpha PLL config. Alpha PLL config was obtained by dumping PLL registers from a running device. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-7-robimarko@gmail.com
* | clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL configRobert Marko2022-09-261-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the IPQ6018 Alpha PLL config to the latest one from the downstream 5.4 kernel[1]. This one should match the production SoC-s. Tested on IPQ6018 CP01-C1 reference board. [1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41 Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-6-robimarko@gmail.com
* | clk: qcom: apss-ipq-pll: use OF match data for Alpha PLL configRobert Marko2022-09-261-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the driver to use OF match data for providing the Alpha PLL config per compatible. This is required for IPQ8074 support since it uses a different Alpha PLL config. While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make it clear that it is for IPQ6018 only. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-5-robimarko@gmail.com
* | clk: qcom: apss-ipq6018: mark apcs_alias0_core_clk as criticalRobert Marko2022-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While fixing up the driver I noticed that my IPQ8074 board was hanging after CPUFreq switched the frequency during boot, WDT would eventually reset it. So mark apcs_alias0_core_clk as critical since its the clock feeding the CPU cluster and must never be disabled. Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-3-robimarko@gmail.com
* | clk: qcom: apss-ipq6018: fix apcs_alias0_clk_srcRobert Marko2022-09-261-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While working on IPQ8074 APSS driver it was discovered that IPQ6018 and IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is currently broken. More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux clock. However after debugging why it was always stuck at 800Mhz, it was figured out that its not regmap_mux compatible at all. It is a simple mux but it uses RCG2 register layout and control bits, so utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not having to provide a dummy frequency table. While we are here, use ARRAY_SIZE for number of parents. Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards. Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com
* | clk: qcom: clk-rcg2: add rcg2 mux opsChristian Marangi2022-09-262-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An RCG may act as a mux that switch between 2 parents. This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds the CPU cluster clock just switches between XO and the PLL that feeds it. Add the required ops to add support for this special configuration and use the generic mux function to determine the rate. This way we dont have to keep a essentially dummy frequency table to use RCG2 as a mux. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com
* | clk: qcom: lcc-ipq806x: use ARRAY_SIZE for num_parentsChristian Marangi2022-09-261-4/+4
| | | | | | | | | | | | | | | | | | | | Use ARRAY_SIZE for num_parents instead of raw number to prevent any confusion/mistake. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724182329.9891-4-ansuelsmth@gmail.com
* | clk: qcom: lcc-ipq806x: convert to parent dataChristian Marangi2022-09-261-31/+38
| | | | | | | | | | | | | | | | | | | | | | Convert lcc-ipq806x driver to parent_data API. Change parent_name for pll4 to pxo_board to prepare the future to eventually drop the double pxo board clk. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724182329.9891-3-ansuelsmth@gmail.com
* | clk: qcom: lcc-ipq806x: add reset definitionChristian Marangi2022-09-261-0/+7
| | | | | | | | | | | | | | | | | | Add reset definition for lcc-ipq806x. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724182329.9891-2-ansuelsmth@gmail.com
* | clk: qcom: cpu-8996: use constant mask for pmuxDmitry Baryshkov2022-09-261-13/+6
| | | | | | | | | | | | | | | | | | Both pmux instances share the same width and shift. Specify the mask at compile time to simplify functions. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-7-dmitry.baryshkov@linaro.org
* | clk: qcom: cpu-8996: don't store parents in clk_cpu_8996_pmuxDmitry Baryshkov2022-09-261-13/+9
| | | | | | | | | | | | | | | | | | Don't store pointers to parents in struct clk_cpu_8996_pmux. Instead use clk_hw_get_parent_by_index to fetch them. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-6-dmitry.baryshkov@linaro.org
* | clk: qcom: cpu-8996: move ACD logic to clk_cpu_8996_pmux_determine_rateDmitry Baryshkov2022-09-261-5/+2
| | | | | | | | | | | | | | | | | | Rather than telling everybody that we are using PLL as a parent (and using ACD clock instead) properly select ACD as a pmux parent clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-5-dmitry.baryshkov@linaro.org
* | clk: qcom: cpu-8996: declare ACD clocksDmitry Baryshkov2022-09-261-12/+41
| | | | | | | | | | | | | | | | | | To simplify the code, define 1:1 fixed factor clocks to represent the ACD pmux parent. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-4-dmitry.baryshkov@linaro.org
* | clk: qcom: cpu-8996: switch to devm_clk_notifier_registerDmitry Baryshkov2022-09-261-23/+2
| | | | | | | | | | | | | | | | | | Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-3-dmitry.baryshkov@linaro.org
* | clk: qcom: msm8996-cpu: Use parent_data/_hws for all clocksYassine Oudjana2022-09-261-32/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace parent_names in PLLs, secondary muxes and primary muxes with parent_data. For primary muxes there were never any *cl_pll_acd clocks, so instead of adding them, put the primary PLLs in both PLL_INDEX and ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when setting parent since we always want ACD when using the primary PLLs. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> [DB: switch to parent_hws for pmux clocks] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220714100351.1834711-2-dmitry.baryshkov@linaro.org
* | clk: qcom: msm8996-cpu: Convert secondary muxes to clk_regmap_muxYassine Oudjana2022-09-261-32/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | There is nothing special about the secondary muxes, unlike the primary muxes which need some extra logic to handle ACD and switching between primary PLL and secondary mux sources. Turn them into clk_regmap_mux and rename cpu_clk_msm8996_mux into cpu_clk_msm8996_pmux to make it specific to primary muxes. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220621160621.24415-5-y.oudjana@protonmail.com
* | clk: qcom: msm8996-cpu: Unify cluster orderYassine Oudjana2022-09-261-18/+18
| | | | | | | | | | | | | | | | | | | | The power cluster comes before the performance cluster. Make everything in the driver follow this order. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220621160621.24415-4-y.oudjana@protonmail.com
* | clk: qcom: msm8996-cpu: Statically define PLL dividersYassine Oudjana2022-09-261-24/+42
| | | | | | | | | | | | | | | | | | | | This will allow for adding them to clk_parent_data arrays in an upcoming patch. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220621160621.24415-3-y.oudjana@protonmail.com
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-22 11:19:42 +0000