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path: root/drivers/clk/renesas/Kconfig
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* clk: renesas: Add minimal boot support for RZ/G3S SoCClaudiu Beznea2023-10-101-1/+6
| | | | | | | | | | | Add minimal clock and reset support for the RZ/G3S SoC to be able to boot Linux from SD Card/eMMC. This includes necessary core clocks for booting and GIC, SCIF, GPIO, and SD0 module clocks and resets. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231006103959.197485-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*Wolfram Sang2023-02-101-1/+1
| | | | | | | | | | | | | | | | R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support for this SoC. Public users only have ES2 onwards. In addition to the ES1 specific removals, a check for it was added preventing the machine to boot further. It may otherwise inherit wrong clock settings from ES2 which could damage the hardware. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy2022-05-061-0/+5
| | | | | | | | | | The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have any CLK_MON registers. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-11-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda2022-04-291-0/+5
| | | | | | | | Initial CPG support for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add support for RZ/G2UL SoCBiju Das2022-04-131-1/+6
| | | | | | | | | | | | | | | The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are not present on RZ/G2UL. This patch adds minimal clock and reset entries required to boot the system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das2022-02-101-1/+6
| | | | | | | | | | | | | | | | The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add support for R-Car S4-8Yoshihiro Shimoda2021-12-081-0/+5
| | | | | | | | | | Initial CPG support for R-Car S4-8 (r8a779f0). Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-10-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driverYoshihiro Shimoda2021-12-081-2/+6
| | | | | | | | | | | | | According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG driver. [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-9-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Make CLK_R9A06G032 invisibleGeert Uytterhoeven2021-08-131-3/+1
| | | | | | | | | | | | | | When configuring a kernel including support for Renesas ARM/ARM64 Socs, but excluding support for the RZ/N1D SoC, the user is always asked about the RZ/N1D clock driver. As this driver is already auto-selected when building a kernel including support for the RZ/N1D SoC, there is no need to make the CLK_R9A06G032 symbol visible, unless compile-testing. Align the symbol description with the other symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/4f3d30c730c30546f702715ffc648922a8156703.1628672649.git.geert+renesas@glider.be
* clk: renesas: Add support for R9A07G044 SoCLad Prabhakar2021-06-101-0/+5
| | | | | | | | | | | | | Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add CPG core wrapper for RZ/G2L SoCLad Prabhakar2021-06-101-0/+4
| | | | | | | | | | | | Add CPG core wrapper for RZ/G2L family. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779a0: Add SDHI supportWolfram Sang2021-01-121-0/+1
| | | | | | | | We use the shiny new CPG library for that. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Factor out CPG libraryWolfram Sang2021-01-121-0/+4
| | | | | | | | | | | R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but similar enough to reuse code. Introduce a new CPG library, factor out the SD clock handling and hook it to the generic Gen3 CPG driver so we have an equal state. V3U will make use of it in the next patch then. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Update description for RZ/G2Lad Prabhakar2020-09-171-1/+1
| | | | | | | | | | The rcar-gen3-cpg driver is also used on Renesas RZ/G2 SoC's, update the description for the CLK_RCAR_GEN3_CPG config symbol to reflect this. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200911101703.20521-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add support for R-Car V3UYoshihiro Shimoda2020-09-171-0/+5
| | | | | | | | | | | | Initial support for R-Car V3U (r8a779a0), including core, module clocks, resets, and register access, because register specification differs from R-Car Gen2/3. Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add r8a774e1 supportMarian-Cristian Rotariu2020-07-131-0/+5
| | | | | | | | | | | Add support for the RZ/G2H (R8A774E1) SoC to the Renesas Clock Pulse Generator / Module Standby and Software Reset driver. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594138692-16816-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com [geert: Mark RWDT critical, cfr. commit f23f1101ad0ef1ac ("clk: renesas: rcar-gen3: Mark RWDT clocks as critical")] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selectsGeert Uytterhoeven2020-04-301-3/+0
| | | | | | | | | | CLK_RENESAS_CPG_MSSR selects CLK_RENESAS_DIV6, and CLK_RCAR_GEN2_CPG selects CLK_RENESAS_CPG_MSSR, so there is no longer a need for the individual R-Car Gen2 clock driver options to select CLK_RENESAS_DIV6. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200427193446.29738-1-geert+renesas@glider.be
* clk: renesas: cpg-mssr: Add R8A7742 supportLad Prabhakar2020-04-301-0/+5
| | | | | | | | | | | Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1587998460-7804-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-usb2-clock-sel: Add reset_controlYoshihiro Shimoda2020-03-091-0/+1
| | | | | | | | | This hardware needs to deassert resets of both host and peripheral. So, this patch adds reset control. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Remove use of ARCH_R8A7795Geert Uytterhoeven2020-02-211-1/+1
| | | | | | | | | CONFIG_ARCH_R8A7795 was split in CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951 in commit b925adfceb529389 ("soc: renesas: Add ARCH_R8A7795[01] for existing R-Car H3"), so its users can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200218112525.5834-1-geert+renesas@glider.be
* clk: renesas: Prepare for split of R-Car H3 config symbolGeert Uytterhoeven2020-01-081-1/+1
| | | | | | | | | | | | | | | | Despite using the same compatible values ("r8a7795"-based) because of historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, with different part numbers. Hence the SoC configuration symbol will be split in two separate config symbols. As the Clock Pulse Generator / Module Standby and Software Reset blocks in both SoCs are very similar, they will keep on sharing a driver. Extend the dependency of CONFIG_CLK_R8A7795, to prepare for the split. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20191230080902.2832-1-geert+renesas@glider.be
* clk: renesas: Remove use of ARCH_R8A7796Geert Uytterhoeven2019-12-131-1/+1
| | | | | | | | | CONFIG_ARCH_R8A7796 was renamed to CONFIG_ARCH_R8A77960 in commit 39e57e14d7eaf818 ("soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W"), so its users can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191211100220.6854-1-geert+renesas@glider.be
* clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportGeert Uytterhoeven2019-11-011-0/+5
| | | | | | | | | | | | | | | | | Add support for the R-Car M3-W+ (R8A77961) SoC to the Renesas Clock Pulse Generator / Module Standby and Software Reset driver. R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. R-Car M3-W+ lacks a few modules, so their clocks must be nullified. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122941.12342-5-geert+renesas@glider.be
* clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960Geert Uytterhoeven2019-11-011-2/+2
| | | | | | | | | | | | | | Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_CLK_R8A77961. Extend the dependency of CONFIG_CLK_R8A77960 from CONFIG_ARCH_R8A7796 to CONFIG_ARCH_R8A77960, to relax dependencies for a future rename of the SoC configuration symbol. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122941.12342-4-geert+renesas@glider.be
* clk: renesas: cpg-mssr: Add r8a774b1 supportBiju Das2019-10-011-0/+5
| | | | | | | | | | | | Add RZ/G2N (R8A774B1) Clock Pulse Generator / Module Standby and Software Reset support. Based on the Table 8.4d of "RZ/G Series, 2nd Generation User's Manual: Hardware (Rev. 0.80, May 2019)". Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1568881036-4404-7-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Remove R-Car Gen2 legacy DT clock supportGeert Uytterhoeven2019-10-011-20/+0
| | | | | | | | | | | | | | | As of commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files use the unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. Hence remove backward compatibility with old R-Car Gen2 device trees describing a hierarchical representation of the various CPG and MSTP clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190830133615.11274-1-geert+renesas@glider.be
* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-181-1/+16
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
| * clk: renesas: cpg-mssr: Add r8a774c0 supportFabrizio Castro2018-09-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and Software Reset support. Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual: Hardware (Rev. 0.61, June 12, 2018)". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7743: Add r8a7744 supportBiju Das2018-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software Reset support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt2018-09-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module Standby. The Module Standby HW in the RZ/A series is very close to R-Car HW, except for how the registers are laid out. The MSTP registers are only 8-bits wide, there are no status registers (MSTPSR), and the register offsets are a little different. Since the RZ/A hardware manuals refer to these registers as the Standby Control Registers, we'll use that name to distinguish the RZ/A type from the R-Car type. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Rob Herring <robh@kernel.org> # DT bits Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: cpg-mssr: Add r8a774a1 supportBiju Das2018-08-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software Reset support. Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual: Hardware ((Rev. 0.61, June 12, 2018)". Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: Convert to SPDX identifiersKuninori Morimoto2018-09-281-0/+2
|/ | | | | | | | | | | This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [rebased against clk-spdx] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: renesas: Renesas R9A06G032 clock driverMichel Pollet2018-06-251-0/+6
| | | | | | | | | This provides a clock driver for the Renesas R09A06G032. This uses a structure derived from both the R-Car Gen2 driver as well as the renesas-cpg-mssr driver. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add support for R-Car E3Yoshihiro Shimoda2018-05-091-0/+5
| | | | | | | | | | | | | Initial support for R-Car E3 (r8a77990), including core and module clocks. Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual: Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018". Inspried by patches by Takeshi Kihara in the BSP. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add r8a77470 supportBiju Das2018-04-161-0/+5
| | | | | | | | | Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and Software Reset support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add support for R-Car M3-NJacopo Mondi2018-02-261-0/+5
| | | | | | | | | | | Initial support for R-Car M3-N (r8a77965), including core and module clocks. Based on Table 8.2d of "R-Car Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct 31, 2017)". Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: add R8A77980 supportSergei Shtylyov2018-02-201-0/+5
| | | | | | | | | | | | | | Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 code. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Stop enabling legacy DT clock support by defaultGeert Uytterhoeven2018-02-121-1/+2
| | | | | | | | Since v4.15-rc1, the DTS files for all R-Car Gen2 SoCs have been converted to the new CPG/MSSR bindings. Hence it is now safe to no longer enable legacy DT clock support by default. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add R8A77970 supportSergei Shtylyov2017-09-191-0/+5
| | | | | | | | | | | | | Add R-Car V3M (R8A77970) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 code. Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHYYoshihiro Shimoda2017-08-171-0/+5
| | | | | | | | | | R-Car USB 2.0 controller can change the clock source from an oscillator to an external clock via a register. So, this patch adds support the clock source selector as a clock driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add R8A77995 supportGeert Uytterhoeven2017-08-161-0/+5
| | | | | | | | | | | | | Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 CPG code. Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev. 0.55, Jun. 30, 2017. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org>
* clk: renesas: Allow compile-testing of all (sub)driversGeert Uytterhoeven2017-07-171-19/+19
| | | | | | | | | | Enable compile-testing of the remaining clock drivers and subdrivers, now dummies are available for of_clk_get_from_provider(), of_device_compatible_match(), and rcar_rst_read_mode_pins(), and the CPG/MSSR driver core has been converted from of_match_node() to of_device_get_match_data(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7794: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-241-2/+3
| | | | | | | | | | | Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7792: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-241-2/+3
| | | | | | | | | | | Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-241-2/+3
| | | | | | | | | | | | Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7790: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-241-1/+12
| | | | | | | | | | | Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Rework Kconfig and Makefile logicGeert Uytterhoeven2017-05-241-15/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC (which may change in the future), - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies. This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol CLK_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/clk/renesas/ during the build. Note that currently not all (sub)drivers are enabled for compile-testing, as they depend on independent fixes in other subsystems. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: cpg-mssr: Add R8A7745 supportSergei Shtylyov2016-11-101-0/+1
| | | | | | | | | | | | | Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add R8A7743 supportSergei Shtylyov2016-11-101-0/+1
| | | | | | | | | | | | | Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add R8A7792 supportSergei Shtylyov2016-06-211-0/+1
| | | | | | | Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-14 20:14:06 +0000