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path: root/drivers/clk/renesas
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* clk: renesas: mstp: Support 8-bit registers for r7s72100Chris Brandt2016-12-211-5/+22
| | | | | | | | | | | | | The RZ/A1 is different than the other Renesas SOCs because the MSTP registers are 8-bit instead of 32-bit and if you try writing values as 32-bit nothing happens...meaning this driver never worked for r7s72100. Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: cpg-mssr: Add R8A7745 supportSergei Shtylyov2016-11-105-0/+268
| | | | | | | | | | | | | Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add R8A7743 supportSergei Shtylyov2016-11-105-0/+279
| | | | | | | | | | | | | Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add common R-Car Gen2 supportSergei Shtylyov2016-11-102-0/+414
| | | | | | | | | | | | Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module Standby and Software Reset support code, using the CPG/MSSR driver core. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Fix HDMI parent clockTakeshi Kihara2016-11-071-1/+1
| | | | | | | | | | Correct HDMI parent clock so that the rate of the HDMI clock is 1/4 rather than 1/2 of the rate of PLL1 as per the v0.52 (Jun, 15) manual. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add VIN clocksNiklas Söderlund2016-11-071-0/+8
| | | | | Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add CSI2 clocksNiklas Söderlund2016-11-071-0/+4
| | | | | Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Merge branch 'rcar-rst' into clk-renesas-for-v4.10Geert Uytterhoeven2016-11-027-51/+59
|\ | | | | | | soc: renesas: Add R-Car RST driver for obtaining mode pin state
| * clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()Geert Uytterhoeven2016-11-021-7/+0
| | | | | | | | | | | | | | The R-Car Gen2 board code no longer calls rcar_gen2_clocks_init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
| * clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init()Geert Uytterhoeven2016-11-021-9/+0
| | | | | | | | | | | | | | The R-Car H1 board code no longer calls r8a7779_clocks_init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
| * clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()Geert Uytterhoeven2016-11-021-13/+0
| | | | | | | | | | | | | | The R-Car M1A board code no longer calls r8a7778_clocks_init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
| * clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()Geert Uytterhoeven2016-11-022-18/+0
| | | | | | | | | | | | | | | | | | All R-Car Gen3 clock drivers now obtain the values of the mode pins from the R-Car RST driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driverGeert Uytterhoeven2016-11-021-1/+7
| | | | | | | | | | | | | | | | | | Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RST module. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driverGeert Uytterhoeven2016-11-021-1/+7
| | | | | | | | | | | | | | | | | | Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RST module. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * clk: renesas: rcar-gen2: Obtain mode pin values using RST driverGeert Uytterhoeven2016-11-021-0/+25
| | | | | | | | | | | | | | | | | | | | | | Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RST module. Fall back to our own private copy of rcar_gen2_read_mode_pins() for backward-compatibility with old DTs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
| * clk: renesas: r8a7779: Obtain mode pin values from R-Car RST driverGeert Uytterhoeven2016-11-021-2/+7
| | | | | | | | | | | | | | | | Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RESET/WDT module. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
| * clk: renesas: r8a7778: Obtain mode pin values using R-Car RST driverGeert Uytterhoeven2016-11-021-0/+13
| | | | | | | | | | | | | | | | Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RESET/WDT module. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* | clk: renesas: r8a7796: Add DU and LVDS clocksLaurent Pinchart2016-11-021-0/+4
| | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7796: Add VSP clocksLaurent Pinchart2016-11-021-0/+5
| | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7796: Add FCP clocksLaurent Pinchart2016-11-021-0/+8
| | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: cpg-mssr: Remove bogus commas from error messagesGeert Uytterhoeven2016-11-021-2/+2
| | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7796: Add DRIF clockRamesh Shanmugasundaram2016-11-021-0/+8
| | | | | | | | | | | | | | | | This patch adds DRIF module clocks for r8a7796 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: cpg-mssr: Fix inverted debug checkGeert Uytterhoeven2016-10-171-2/+2
| | | | | | | | | | | | | | | | The intention was to enable the checks if debugging is enabled, not disabled. Fixes: f793d1e51705b276 ("clk: shmobile: Add new CPG/MSSR driver core") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: rcar-gen3-cpg: Always use readl()/writel()Geert Uytterhoeven2016-10-171-7/+7
| | | | | | | | | | | | | | | | | | The R-Car Gen3 CPG/MSSR driver uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: renesas: cpg-mssr: Always use readl()/writel()Geert Uytterhoeven2016-10-171-5/+4
| | | | | | | | | | | | | | | | | | The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: renesas: r8a7796: Add I2C clocksUlrich Hecht2016-10-171-0/+7
| | | | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7796: Add HSCIF clocksUlrich Hecht2016-10-171-0/+5
| | | | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7796: Add SCIF clocksUlrich Hecht2016-10-171-0/+5
| | | | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7796: Add SYS-DMAC clocksUlrich Hecht2016-10-171-0/+3
|/ | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk/Renesas-MSTP: Use kmalloc_array() in cpg_mstp_clocks_init()Markus Elfring2016-09-161-1/+1
| | | | | | | | | | | | A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kmalloc_array". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'clk-renesas-for-v4.9-tag3' of ↵Stephen Boyd2016-09-143-2/+32
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk driver updates from Geert Uytterhoeven: - External crystal selection for RZ/A1, - CMT clocks for R-Car H3 and M3-W, - RAVB and Thermal clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add CMT clocks clk: renesas: r8a7795: Add CMT clocks clk: renesas: r8a7796: Add RAVB clock clk: renesas: r8a7796: Add THS/TSC clock clk: renesas: rz: Select EXTAL vs USB clock
| * clk: renesas: r8a7796: Add CMT clocksBui Duc Phuc2016-09-121-0/+4
| | | | | | | | | | | | | | This patch adds CMT module clocks for r8a7796 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7795: Add CMT clocksBui Duc Phuc2016-09-121-0/+4
| | | | | | | | | | | | | | This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7796: Add RAVB clockLaurent Pinchart2016-09-121-0/+1
| | | | | | | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7796: Add THS/TSC clockKhiem Nguyen2016-09-051-0/+1
| | | | | | | | | | Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: rz: Select EXTAL vs USB clockChris Brandt2016-09-051-2/+22
| | | | | | | | | | | | | | | | Check the MD_CLK pin to determine the current clock mode in order to set the pll clock parent correctly. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | Merge tag 'clk-renesas-for-v4.9-tag2' of ↵Stephen Boyd2016-08-301-0/+18
|\| | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas r8a7796 SDHI clock support from Geert Uytterhoeven: Add all clocks needed to use the SDHI interfaces on the Renesas R-Car M3-W (r8a7796) SoC. * tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add SDIF clocks clk: renesas: r8a7796: Add GPIO clocks
| * clk: renesas: r8a7796: Add SDIF clocksSimon Horman2016-08-231-0/+10
| | | | | | | | | | | | | | | | | | This patch adds SDIF clocks for R8A7796 SoC. Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7796: Add GPIO clocksTakeshi Kihara2016-08-191-0/+8
| | | | | | | | | | | | | | | | Add GPIO clocks for the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | Merge tag 'clk-renesas-for-v4.9-tag1' of ↵Stephen Boyd2016-08-181-0/+7
|\| | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Merge r8a7796 watchdog clk support from Geert Uytterhoeven: Add all clocks related to the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. * tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add watchdog module clock clk: renesas: r8a7796: Add watchdog core clocks
| * clk: renesas: r8a7796: Add watchdog module clockGeert Uytterhoeven2016-08-091-0/+1
| | | | | | | | | | | | | | Add the module clock for the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7796: Add watchdog core clocksGeert Uytterhoeven2016-08-091-0/+6
| | | | | | | | | | | | | | Add all core clocks related to the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7795: Fix SD clocksYoshihiro Shimoda2016-08-111-4/+5
|/ | | | | | | | | | | | | | | | According to the datasheet, SDn clocks are from the SDSRC clock. And the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal core clock. Otherwise, since the sdhi driver will calculate clock for a sd card using the wrong parent clock rate, and then performance will be not good. Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: r8a7795: Add THS/TSC clockKhiem Nguyen2016-06-211-0/+1
| | | | | Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add DRIF clockRamesh Shanmugasundaram2016-06-211-0/+8
| | | | | | | This patch adds DRIF module clocks for r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Correct lvds clock parentGeert Uytterhoeven2016-06-211-1/+1
| | | | | | | | | | | According to the latest information, the parent clock of the LVDS module clock is the S0D4 clock, not the S2D1 clock. Note that this change has no influence on actual operation, as the rcar-du LVDS encoder driver doesn't use the parent clock's rate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* clk: renesas: r8a7795: Provide FDP1 clocksKieran Bingham2016-06-211-0/+3
| | | | | | Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran@bingham.xyz> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add R8A7792 supportSergei Shtylyov2016-06-212-0/+2
| | | | | | | Renesas R-Car V2H (R8A7792) clocks are handled by R-Car gen2 clock driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add support for R-Car M3-WGeert Uytterhoeven2016-06-065-0/+201
| | | | | | | | Initial support for R-Car M3-W (r8a7796), including basic core clocks, and SCIF2 (console) and INTC-AP (GIC) module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: cpg-mssr: Extract common R-Car Gen3 support codeGeert Uytterhoeven2016-06-064-356/+408
| | | | | | | | | | | | | Extract the code to support parts common to all members of the R-Car Gen3 SoC family into a separate file, to ease sharing among SoC-specific drivers. Note that while the cpg_pll_configs[] arrays and the selection of the config based on the MODE bits are identical on R-Car H3 and R-Car M3-W, they are not common, and may be different on other R-Car Gen3 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
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