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path: root/drivers/clk/rockchip/clk-rk3399.c
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* clk: rockchip: drop module parts from rk3399 and rk3568 driversHeiko Stuebner2021-11-021-4/+0
* Revert "clk: rockchip: use module_platform_driver_probe"Heiko Stuebner2021-11-021-1/+1
* clk: rockchip: use module_platform_driver_probeMiles Chen2021-09-211-1/+1
* clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}Brian Norris2021-09-201-2/+2
* clk: rockchip: rk3399: make CPU clocks criticalBrian Norris2021-09-201-4/+7
* clk: rockchip: drop MODULE_ALIAS from rk3399 clock controllerHeiko Stuebner2021-03-211-1/+0
* clk: rockchip: support more core div settingElaine Zhang2021-03-211-6/+8
* clk: rockchip: rk3399: Support module buildElaine Zhang2020-09-221-0/+56
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-9/+3
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| * clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macroHeiko Stuebner2019-06-151-9/+3
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-10/+1
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* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399Levin Du2018-08-061-0/+1
* clk: rockchip: fix clk_i2sout parent selection bits on rk3399Alberto Panizzo2018-07-081-1/+1
* clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399Lin Huang2018-03-231-2/+2
* clk: rockchip: Add 1.6GHz PLL rate for rk3399Derek Basehore2018-03-141-0/+1
* clk: rockchip: add ids for rk3399 testclks used for camera handlingEddie Cai2017-06-021-2/+2
* clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399Douglas Anderson2017-03-061-4/+4
* clk: rockchip: fix the incorrect pclk_edp div width for RK3399Xing Zheng2017-01-181-1/+1
* clk: rockchip: fix copy-paste error in rk3399 testclkJianqun Xu2016-11-161-2/+2
* clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktreeJianqun Xu2016-11-051-11/+11
* clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399Xing Zheng2016-11-021-2/+2
* clk: rockchip: add 533.25MHz to rk3399 clock rates tableXing Zheng2016-10-211-0/+1
* Merge tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/g...Stephen Boyd2016-09-061-15/+41
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| * clk: rockchip: use the dclk_vop_frac clock ids on rk3399Yakir Yang2016-09-041-2/+2
| * clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividersDouglas Anderson2016-09-041-13/+13
| * clk: rockchip: add 2016M to big cpu clk rate table on rk3399Shunqian Zheng2016-09-041-0/+1
| * clk: rockchip: add rk3399 ddr clock supportLin Huang2016-09-041-0/+19
| * clk: rockchip: mark rk3399 hdcp_noc and vio_noc as criticalChris Zhong2016-08-121-0/+4
| * clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399Elaine Zhang2016-08-081-2/+2
| * clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMIXing Zheng2016-08-081-0/+2
* | clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399Xing Zheng2016-08-241-0/+1
* | clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399Xing Zheng2016-08-121-2/+2
* | clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399Xing Zheng2016-08-121-2/+2
* | clk: rockchip: fix rk3399 aclk_vio gate bitChris Zhong2016-08-111-1/+1
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* Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/g...Stephen Boyd2016-07-011-1/+10
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| * clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bitsXing Zheng2016-07-011-1/+1
| * clk: rockchip: add a dummy clock for the watchdog pclk on rk3399Xing Zheng2016-05-301-0/+9
* | clk: rockchip: release io resource when failing to init clk on rk3399Shawn Lin2016-06-031-0/+2
* | clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_srcXing Zheng2016-05-301-2/+2
* | clk: rockchip: mark rk3399 GIC clocks as criticalBrian Norris2016-05-301-0/+2
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* clk: rockchip: fix the rk3399 sdmmc sample / drv nameDouglas Anderson2016-05-081-2/+2
* clk: rockchip: fix the rk3399 cifout clockXing Zheng2016-04-251-5/+6
* clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399Xing Zheng2016-04-251-157/+157
* clk: rockchip: add some frequencies on the rk3399 PLL tableXing Zheng2016-04-251-1/+10
* clk: rockchip: assign more necessary rk3399 clock idsXing Zheng2016-04-251-6/+6
* clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399Xing Zheng2016-04-251-2/+2
* clk: rockchip: reign in some overly long lines in the rk3399 controllerHeiko Stuebner2016-04-191-58/+81
* clk: rockchip: add clock controller for the RK3399Xing Zheng2016-03-281-0/+1540
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 23:08:10 +0000