summaryrefslogtreecommitdiffstats
path: root/drivers/clk/sunxi/clk-sunxi.c
Commit message (Expand)AuthorAgeFilesLines
* clk: sunxi: Fix of_io_request_and_map error checkMaxime Ripard2015-05-051-0/+2
* clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6Chen-Yu Tsai2015-03-251-1/+2
* clk: sunxi: Make divs clocks specify which output is the base factor clockChen-Yu Tsai2015-03-251-12/+25
* clk: sunxi: Register divs clocks before factor clocksChen-Yu Tsai2015-03-211-3/+3
* clk: sunxi: Add "cpu" to list of protected clocks for sun5iChen-Yu Tsai2015-03-211-0/+1
* clk: sunxi: Add muxable ahb factors clock for sun5i and sun7iChen-Yu Tsai2015-03-211-0/+52
* clk: sunxi: Move USB clocks to separate fileChen-Yu Tsai2015-02-231-88/+0
* Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds2015-02-211-40/+222
|\
| * clk: Add rate constraints to clocksTomeu Vizoso2015-02-021-0/+2
| * sunxi: clk: Set sun6i-pll1 n_start = 1Hans de Goede2015-01-251-0/+1
| * clk: sunxi: Remove custom phase functionMaxime Ripard2015-01-141-37/+0
| * clk: sunxi: Propagate rate changes to parent for mux clocksChen-Yu Tsai2015-01-061-1/+1
| * clk: sunxi: Give sunxi_factors_register a registers parameterHans de Goede2014-12-211-1/+10
| * clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai2014-12-211-0/+208
| * clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks listChen-Yu Tsai2014-12-211-1/+0
* | ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxiHans de Goede2015-01-051-0/+1
|/
* clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai2014-11-231-12/+16
* clk: sunxi: Specify number of child clocks for divs clocksChen-Yu Tsai2014-11-231-2/+9
* clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai2014-11-231-7/+0
* clk: sunxi: unify APB1 clockEmilio López2014-11-111-5/+2
* clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai2014-10-211-0/+31
* clk: sunxi: make factors clock mux mask configurableChen-Yu Tsai2014-10-211-0/+1
* clk: sunxi: Move mbus to mod0 fileMaxime Ripard2014-09-271-57/+0
* clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard2014-09-271-1/+0
* clk: sunxi: Introduce mbus compatibleMaxime Ripard2014-09-271-0/+1
* clk: sunxi: factors: Invert the probing logicMaxime Ripard2014-09-271-92/+3
* clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai2014-09-131-0/+9
* clk: sunxi: add __iomem markings to MMIO pointersEmilio López2014-07-281-5/+5
* clk: sunxi: Add A23 clocks supportChen-Yu Tsai2014-07-041-0/+101
* clk: sunxi: Add support for table-based divider clocksChen-Yu Tsai2014-07-041-4/+5
* clk: sunxi: move "ahb_sdram" to protected clock listChen-Yu Tsai2014-07-041-5/+3
* clk: sunxi: register clock gates with clkdevChen-Yu Tsai2014-07-041-0/+1
* clk: sun6i: Protect SDRAM gating bitMaxime Ripard2014-06-111-0/+1
* clk: sun6i: Protect CPU clockMaxime Ripard2014-06-111-0/+1
* clk: sunxi: Rework clock protection codeMaxime Ripard2014-06-111-28/+44
* clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard2014-06-111-98/+0
* clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard2014-06-111-57/+0
* clk: sunxi: Remove calls to clk_putMaxime Ripard2014-06-111-6/+2
* clk: sunxi: Implement A31 USB clockMaxime Ripard2014-06-111-0/+6
* Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds2014-06-071-0/+37
|\
| * clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clkHans de Goede2014-05-141-1/+2
| * clk: sunxi: Implement MMC phase controlEmilio López2014-05-051-0/+36
* | clk: sunxi: fix function type for CLK_OF_DECLARERob Herring2014-05-201-1/+1
* | clk: sunxi: avoid double DT matchingRob Herring2014-05-201-2/+1
|/
* clk: sunxi: fix thinko in commentEmilio López2014-03-191-1/+1
* clk: sunxi: fix some calculationsEmilio López2014-03-191-3/+3
* clk: sunxi: fix A20 PLL4 calculationEmilio López2014-03-191-0/+7
* clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-181-15/+15
* clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-181-0/+96
* clk: sunxi: Add support for PLL6 on the A31Maxime Ripard2014-02-181-0/+45
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-01 08:40:29 +0000