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path: root/drivers/clk/sunxi
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* clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6Chen-Yu Tsai2015-03-251-1/+2
* clk: sunxi: Make divs clocks specify which output is the base factor clockChen-Yu Tsai2015-03-251-12/+25
* clk: sunxi: Register divs clocks before factor clocksChen-Yu Tsai2015-03-211-3/+3
* clk: sunxi: Add "cpu" to list of protected clocks for sun5iChen-Yu Tsai2015-03-211-0/+1
* clk: sunxi: Add muxable ahb factors clock for sun5i and sun7iChen-Yu Tsai2015-03-211-0/+52
* clk: sunxi: Add support for sun9i A80 USB clocks and resetsChen-Yu Tsai2015-02-231-0/+43
* clk: sunxi: Move USB clocks to separate fileChen-Yu Tsai2015-02-233-88/+191
* Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds2015-02-219-143/+716
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| * clk: Add rate constraints to clocksTomeu Vizoso2015-02-023-0/+6
| * sunxi: clk: Set sun6i-pll1 n_start = 1Hans de Goede2015-01-251-0/+1
| * clk: sunxi: rewrite sun9i_a80_get_pll4_factors()Hans de Goede2015-01-251-28/+29
| * clk: sunxi: Add driver for A80 MMC config clocks/resetsChen-Yu Tsai2015-01-202-0/+220
| * clk: sunxi: Add mod0 and mmc module clock support for A80Chen-Yu Tsai2015-01-191-0/+32
| * clk: sunxi: Add a common setup function for mmc module clocksChen-Yu Tsai2015-01-141-7/+19
| * clk: sunxi: Remove custom phase functionMaxime Ripard2015-01-141-37/+0
| * clk: sunxi: Rework MMC phase clocksMaxime Ripard2015-01-141-62/+69
| * clk: sunxi: Propagate rate changes to parent for mux clocksChen-Yu Tsai2015-01-061-1/+1
| * clk: sunxi: Make the mod0 clk driver also a platform driverHans de Goede2015-01-061-3/+40
| * clk: sunxi: Fix factor clocks usage for sun9i core clocksChen-Yu Tsai2014-12-211-6/+56
| * clk: sunxi: Give sunxi_factors_register a registers parameterHans de Goede2014-12-215-14/+51
| * clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai2014-12-211-0/+208
| * clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks listChen-Yu Tsai2014-12-211-1/+0
* | ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxiHans de Goede2015-01-051-0/+1
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* clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2014-12-032-4/+4
* clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT muxHans de Goede2014-11-231-1/+6
* clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai2014-11-231-12/+16
* clk: sunxi: Specify number of child clocks for divs clocksChen-Yu Tsai2014-11-231-2/+9
* clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai2014-11-231-7/+0
* clk: sunxi: unify APB1 clockEmilio López2014-11-111-5/+2
* clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai2014-10-211-0/+31
* clk: sunxi: Add support for A80 basic bus clocksChen-Yu Tsai2014-10-212-0/+272
* clk: sunxi: make factors clock mux mask configurableChen-Yu Tsai2014-10-215-3/+5
* Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kerne...Mike Turquette2014-09-276-156/+485
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| * clk: sunxi: Add sun8i MBUS clock supportChen-Yu Tsai2014-09-272-0/+79
| * clk: sunxi: mod0: Introduce MMC proper phase handlingMaxime Ripard2014-09-271-0/+189
| * clk: sunxi: Move mbus to mod0 fileMaxime Ripard2014-09-272-57/+12
| * clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard2014-09-273-1/+83
| * clk: sunxi: Introduce mbus compatibleMaxime Ripard2014-09-271-0/+1
| * clk: sunxi: factors: Invert the probing logicMaxime Ripard2014-09-273-99/+113
| * clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai2014-09-131-0/+9
* | clk: Remove .owner field for driverKiran Padwal2014-09-254-4/+0
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* clk: sunxi: staticize structures and arraysEmilio López2014-07-284-5/+5
* clk: sunxi: add __iomem markings to MMIO pointersEmilio López2014-07-282-6/+6
* Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kerne...Mike Turquette2014-07-256-43/+227
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| * clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 supportChen-Yu Tsai2014-07-151-0/+5
| * clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indicesChen-Yu Tsai2014-07-151-36/+39
| * clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gatesChen-Yu Tsai2014-07-071-1/+5
| * clk: sunxi: Add A23 APB0 divider clock supportChen-Yu Tsai2014-07-072-1/+71
| * clk: sunxi: Add A23 clocks supportChen-Yu Tsai2014-07-041-0/+101
| * clk: sunxi: Add support for table-based divider clocksChen-Yu Tsai2014-07-041-4/+5
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 14:27:59 +0000