summaryrefslogtreecommitdiffstats
path: root/drivers/clk/tegra
Commit message (Collapse)AuthorAgeFilesLines
...
* | | Merge tag 'tegra-for-5.1-clk' of ↵Arnd Bergmann2019-02-157-98/+913
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers clk: tegra: Changes for v5.1-rc1 This contains a couple of prerequisite patches to enable CPU frequency scaling on Tegra210. * tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 clk: tegra: dfll: add CVB tables for Tegra210 clk: tegra: dfll: round down voltages based on alignment clk: tegra: dfll: support PWM regulator control clk: tegra: dfll: CVB calculation alignment with the regulator clk: tegra: dfll: registration for multiple SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver2019-02-062-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra210 has a DFLL as well and can share the majority of the code with the Tegra124 implementation. So build the same code for both platforms. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo2019-02-062-0/+427
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CVB tables with different chip characterization, so that we can generate the customize OPP table that suitable for different chips with different SKUs. The parameter 'tune_high_min_millivolts' is first time introduced in this patch, which didn't use in the DFLL driver for clock and voltage tuning before. It will be used later when DFLL in high voltage range. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: dfll: round down voltages based on alignmentJoseph Lo2019-02-061-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When generating the OPP table, the voltages are round down with the alignment from the regulator. The alignment should be applied for voltages look up as well. Based on the work of Penny Chiu <pchiu@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: dfll: support PWM regulator controlJoseph Lo2019-02-061-67/+377
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DFLL hardware supports two modes (I2C and PWM) for voltage control when requesting a frequency. In this patch, we introduce PWM mode support. To support that, we re-organize the LUT for unifying the table for both cases of I2C and PWM mode. And generate that based on regulator info. For the PWM-based regulator, we get this info from DT. And do the same as the case of I2C LUT, which can help to map the PMIC voltage ID and voltages that the regulator supported. The other parts are the support code for initializing the DFLL hardware to support PWM mode. Also, the register debugfs file is slightly reworked to only show the i2c registers when I2C mode is in use. Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo2019-02-064-14/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CVB table contains calibration data for the CPU DFLL based on process characterization. The regulator step and offset parameters depend on the regulator supplying vdd-cpu, not on the specific Tegra SKU. When using a PWM controlled regulator, the voltage step and offset are determined by the regulator type in use. This is specified in DT. When using an I2C controlled regulator, we can retrieve them from CPU regulator Then pass this information to the CVB table calculation function. Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>" and "Alex Frid <afrid@nvidia.com>". Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver2019-02-061-11/+34
| |/ | | | | | | | | | | | | | | | | | | | | | | In a future patch, support for the DFLL in Tegra210 will be introduced. This requires support for more than 1 set of CVB and CPU max frequency tables. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* / clk: tegra: dfll: Fix a potential Oop in remove()Dan Carpenter2019-01-091-1/+3
|/ | | | | | | | | If tegra_dfll_unregister() fails then "soc" is an error pointer. We should just return instead of dereferencing it. Fixes: 1752c9ee23fb ("clk: tegra: dfll: Fix drvdata overwriting issue") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
*-. Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and ↵Stephen Boyd2018-12-1410-32/+80
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-rockchip' into clk-next * clk-renesas: clk: renesas: rcar-gen3: Add HS400 quirk for SD clock clk: renesas: rcar-gen3: Add documentation for SD clocks clk: renesas: rcar-gen3: Set state when registering SD clocks clk: renesas: r8a77995: Simplify PLL3 multiplier/divider clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77990: Correct parent clock of DU clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a774a1: Add CPEX clock dt-bindings: clock: r8a7796: Remove CSIREF clock dt-bindings: clock: r8a7795: Remove CSIREF clock clk: renesas: Mark rza2_cpg_clk_register static clk: renesas: r7s9210: Add USB clocks clk: renesas: r8a77970: Add RPC clocks clk: renesas: r7s9210: Add SDHI clocks * clk-allwinner: clk: sunxi-ng: a64: Allow parent change for VE clock clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL clk: sunxi-ng: h3: Allow parent change for ve clock clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: h6: Set video PLLs limits clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock * clk-tegra: clk: tegra: Return the exact clock rate from clk_round_rate clk: tegra30: Use Tegra CPU powergate helper function soc/tegra: pmc: Drop SMP dependency from CPU APIs clk: tegra: Fix maximum audio sync clock for Tegra124/210 clk: tegra: get rid of duplicate defines clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC clk: tegra20: Turn EMC clock gate into divider * clk-meson: (25 commits) clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: Mark some things static clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width clk: meson: meson8b: add the CPU clock post divider clocks clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 clk: meson: clk-regmap: add read-only gate ops clk: meson: meson8b: allow changing the CPU clock tree clk: meson: meson8b: run from the XTAL when changing the CPU frequency clk: meson: meson8b: add support for more M/N values in sys_pll clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel clk: meson: clk-pll: check if the clock is already enabled clk: meson: meson8b: fix the width of the cpu_scale_div clock clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table clk: meson: meson8b: use the HHI syscon if available dt-bindings: clock: meson8b: use the registers from the HHI syscon ... * clk-rockchip: clk: rockchip: add clock-id to gate of ACODEC for rk3328 clk: rockchip: add clock ID of ACODEC for rk3328 clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328 clk: rockchip: fix I2S1 clock gate register for rk3328 clk: rockchip: make rk3188 hclk_vio_bus critical clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering clk: rockchip: fix rk3188 sclk_smc gate data clk: rockchip: fix typo in rk3188 spdif_frac parent
| | * clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang2018-12-141-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API. Signed-off-by: Robert Yang <decatf@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra30: Use Tegra CPU powergate helper functionJon Hunter2018-12-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than using the tegra_powergate_is_powered() function for determining if a CPU is powered, use the tegra_pmc_cpu_is_powered() instead which was created to get the CPU power status. Internally tegra_pmc_cpu_is_powered() calls tegra_powergate_is_powered() and so is equivalent. The Tegra30 clock driver is the only public user of tegra_powergate_is_powered() and so by updating the Tegra30 clock driver to use tegra_pmc_cpu_is_powered(), we can then make tegra_powergate_is_powered() a non-public function. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter2018-12-147-13/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The maximum frequency supported for I2S on Tegra124 and Tegra210 is 24.576MHz (as stated in the Tegra TK1 data sheet for Tegra124 and the Jetson TX1 module data sheet for Tegra210). However, the maximum I2S frequency is limited to 24MHz because that is the maximum frequency of the audio sync clock. Increase the maximum audio sync clock frequency to 24.576MHz for Tegra124 and Tegra210 in order to support 24.576MHz for I2S. Update the tegra_clk_register_sync_source() function so that it does not set the initial rate for the sync clocks and use the clock init tables to set the initial rate instead. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra: get rid of duplicate definesMarcel Ziswiler2018-12-141-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Get rid of 3 duplicate defines. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra20: Check whether direct PLLM sourcing is turned off for EMCDmitry Osipenko2018-11-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that direct PLLM sourcing is turned off for EMC as we don't support that configuration in the clk driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko2018-11-081-10/+26
| |/ | | | | | | | | | | | | | | | | | | | | | | Kernel should never gate the EMC clock as it causes immediate lockup, so removing clk-gate functionality doesn't affect anything. Turning EMC clk gate into divider allows to implement glitch-less EMC scaling, avoiding reparenting to a backup clock. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* / clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li2018-11-281-11/+1
|/ | | | | | | | Use macro to simplify the code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: tegra210: Include size.h for compilation easeStephen Boyd2018-10-161-0/+1
| | | | | | | | | You can't compile this file by itself because it uses SZ_64K from sizes.h but doesn't include it. Instead it relies on some certain configuration pulling that in implicitly somewhere else. Just add the include to make random compile testing easier. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: tegra: Fixes for MBIST work aroundJoseph Lo2018-10-161-3/+3
| | | | | | | | | | | Fix some incorrect data in LVL2 offset and bit mask. Fixes: e403d0057343 ("clk: tegra: MBIST work around for Tegra210") Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: tegra: probe deferral error reportingMarcel Ziswiler2018-10-161-2/+6
| | | | | | | | | Actually report the error code from devm_regulator_get() which may as well just be a probe deferral. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
*-. Merge branches 'clk-imx6-ocram', 'clk-missing-put', ↵Stephen Boyd2018-08-148-40/+343
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next * clk-imx6-ocram: : - i.MX6SX ocram_s clk support clk: imx: add ocram_s clock for i.mx6sx * clk-missing-put: : - Add missing of_node_put()s in some i.MX clk drivers clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() * clk-tegra-sdmmc-jitter: : - Tegra SDMMC clk jitter improvements with high speed signaling modes clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() * clk-allwinner: clk: sunxi-ng: add A64 compatible string dt-bindings: add compatible string for the A64 DE2 CCU clk: sunxi-ng: r40: Export video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Add minimal rate for video PLLs * clk-uniphier: : - Uniphier NAND, USB3 PHY, and SPI clk support clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock
| | * clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver2018-07-253-15/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These clocks have low jitter paths to certain parents. To model these correctly, use the sdmmc mux divider clock type. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver2018-07-253-0/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra: Refactor fractional divider calculationPeter De Schrijver2018-07-254-25/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo2018-07-251-0/+1
| |/ | | | | | | | | | | | | | | | | | | Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| |
| \
| \
| \
| \
| \
*-----. \ Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', ↵Stephen Boyd2018-08-144-7/+15
|\ \ \ \ \ | |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-tegra-critical' and 'clk-tegra-emc-oob' into clk-next * clk-imx-critical: : - Convert to CLK_IS_CRITICAL for i.MX51/53 driver clk: imx51-imx53: Include sizes.h to silence compile errors clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICAL * clk-tegra-bpmp: : - Fix Tegra BPMP driver oops when some xlating a NULL clk clk: tegra: bpmp: Don't crash when a clock fails to register * clk-tegra-124: : - Proper default configuration for vic03 and vde clks on Tegra124 clk: tegra: Make vde a child of pll_c3 clk: tegra: Make vic03 a child of pll_c3 * clk-tegra-critical: : - Mark Tegra memory controller clks as critical clk: tegra: Mark Memory Controller clock as critical * clk-tegra-emc-oob: : - Fix array bounds clamp in Tegra's emc determine_rate() op clk: tegra: emc: Avoid out-of-bounds bug
| | | | * clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko2018-07-081-1/+1
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently there was an attempt to avoid out-of-bounds accesses when there is only one memory timing available, but there is a typo in the code that neglects that attempt. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko2018-07-081-2/+3
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | Memory Controller should be always-on. Currently the sibling EMC clock is marked as critical, let's mark MC clock too for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra: Make vde a child of pll_c3Thierry Reding2018-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current default is to leave the VDE clock's parent at the default, which is clk_m. However, that is not a configuration that will allow the VDE to function. Reparent it to pll_c3 instead to make sure the hardware can actually decode video content. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: tegra: Make vic03 a child of pll_c3Thierry Reding2018-07-081-0/+1
| |/ |/| | | | | | | | | | | | | | | By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen2018-07-081-3/+9
|/ | | | | | | | | | | | | When registering clocks, we just skip any that fail to register (leaving a NULL hole in the clock table). However, our of_xlate function still tries to dereference each entry while looking for the clock with the requested id, causing a crash if any clocks failed to register. Add a check to of_xlate to skip any NULL clocks. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* treewide: kzalloc() -> kcalloc()Kees Cook2018-06-121-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kzalloc() function has a 2-factor argument form, kcalloc(). This patch replaces cases of: kzalloc(a * b, gfp) with: kcalloc(a * b, gfp) as well as handling cases of: kzalloc(a * b * c, gfp) with: kzalloc(array3_size(a, b, c), gfp) as it's slightly less ugly than: kzalloc_array(array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: kzalloc(4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ type TYPE; expression THING, E; @@ ( kzalloc( - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | kzalloc( - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression COUNT; typedef u8; typedef __u8; @@ ( kzalloc( - sizeof(u8) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(__u8) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(char) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(unsigned char) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(u8) * COUNT + COUNT , ...) | kzalloc( - sizeof(__u8) * COUNT + COUNT , ...) | kzalloc( - sizeof(char) * COUNT + COUNT , ...) | kzalloc( - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - kzalloc + kcalloc ( - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ identifier SIZE, COUNT; @@ - kzalloc + kcalloc ( - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( kzalloc( - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( kzalloc( - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | kzalloc( - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | kzalloc( - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ identifier STRIDE, SIZE, COUNT; @@ ( kzalloc( - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression E1, E2, E3; constant C1, C2, C3; @@ ( kzalloc(C1 * C2 * C3, ...) | kzalloc( - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | kzalloc( - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | kzalloc( - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | kzalloc( - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( kzalloc(sizeof(THING) * C2, ...) | kzalloc(sizeof(TYPE) * C2, ...) | kzalloc(C1 * C2 * C3, ...) | kzalloc(C1 * C2, ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - kzalloc + kcalloc ( - (E1) * E2 + E1, E2 , ...) | - kzalloc + kcalloc ( - (E1) * (E2) + E1, E2 , ...) | - kzalloc + kcalloc ( - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
*-. Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' ↵Stephen Boyd2018-06-041-31/+11
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'clk-debugfs-simple' into clk-next * clk-imx7d: clk: imx7d: reset parent for mipi csi root clk: imx7d: fix mipi dphy div parent * clk-hisi-stub: clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB * clk-mvebu: clk: mvebu: use correct bit for 98DX3236 NAND * clk-imx6-epit: clk: imx6: add EPIT clock support * clk-debugfs-simple: clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions
| | * clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman2018-06-011-31/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. The return value of these functions were never checked in the end anyway, so it is obvious this does not change any functionality :) Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-187-8/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user may expect parent clock to be enabled by the child, so let's return -EPROBE_DEFER till parent clock appears. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko2018-05-181-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parents of CDEV1/2 clocks are determined by muxing of the corresponding pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the corresponding muxes to fix the parents. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko2018-05-181-0/+14
|/ | | | | | | | | | | | | | CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as a parent. Add these dividers in order to be able to provide that parent option. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Fix pll_u rate configurationMarcel Ziswiler2018-03-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turns out latest upstream U-Boot does not configure/enable pll_u which leaves it at some default rate of 500 kHz: root@apalis-t30:~# cat /sys/kernel/debug/clk/clk_summary | grep pll_u pll_u 3 3 0 500000 0 Of course this won't quite work leading to the following messages: [ 6.559593] usb 2-1: new full-speed USB device number 2 using tegra- ehci [ 11.759173] usb 2-1: device descriptor read/64, error -110 [ 27.119453] usb 2-1: device descriptor read/64, error -110 [ 27.389217] usb 2-1: new full-speed USB device number 3 using tegra- ehci [ 32.559454] usb 2-1: device descriptor read/64, error -110 [ 47.929777] usb 2-1: device descriptor read/64, error -110 [ 48.049658] usb usb2-port1: attempt power cycle [ 48.759475] usb 2-1: new full-speed USB device number 4 using tegra- ehci [ 59.349457] usb 2-1: device not accepting address 4, error -110 [ 59.509449] usb 2-1: new full-speed USB device number 5 using tegra- ehci [ 70.069457] usb 2-1: device not accepting address 5, error -110 [ 70.079721] usb usb2-port1: unable to enumerate USB device Fix this by actually allowing the rate also being set from within the Linux kernel. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Specify VDE clock rateDmitry Osipenko2018-03-124-1/+4
| | | | | | | | | | Currently VDE clock rate is determined by clock config left from bootloader, let's not rely on it and explicitly specify the clock rate in the CCF driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko2018-03-121-3/+3
| | | | | | | | | PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's set it to 240 MHz and explicitly specify HCLK rate for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-128-36/+26
| | | | | | | | | | Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks as critical. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: <stable@vger.kernel.org> # v4.16 Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: MBIST work around for Tegra210Peter De Schrijver2018-03-081-2/+342
| | | | | | | | | | | | | | | | | | | | | | Tegra210 has a hw bug which can cause IP blocks to lock up when ungating a domain. The reason is that the logic responsible for resetting the memory built-in self test mode can come up in an undefined state because its clock is gated by a second level clock gate (SLCG). Work around this by making sure the logic will get some clock edges by ensuring the relevant clock is enabled and temporarily override the relevant SLCGs. Unfortunately for some IP blocks, the control bits for overriding the SLCGs are not in CAR, but in the IP block itself. This means we need to map a few extra register banks in the clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> fixup mbist
* clk: tegra: add fence_delay for clock registersPeter De Schrijver2018-03-081-0/+7
| | | | | | | | | | | | | | To ensure writes to clock registers have properly propagated through the clock control logic and state machines, we need to ensure the writes have been posted in the registers and wait for 1us after that. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add la clock for Tegra210Peter De Schrijver2018-03-081-0/+14
| | | | | | | | | | | | This clock is needed by the memory built-in self test work around. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-11-1713-66/+102
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have two changes to the core framework this time around. The first being a large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Summary: Core: - runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - runtime PM support for Samsung exynos5433/exynos4412 providers - removal of clkdev aliases on Samsung SoCs - convert clk-gpio to use gpio descriptors - various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - support for the second display unit clock on Renesas RZ/G1E - suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - new clock ids for Rockchip rk3188 and rk3368 SoCs - various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: stm32h7: fix test of clock config clk: pxa: fix building on older compilers clk: sunxi-ng: a83t: Fix i2c buses bits clk: ti: dra7-atl-clock: fix child-node lookups clk: qcom: common: fix legacy board-clock registration clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: kona-setup: Delete error messages for failed memory allocations ARC: clk: fix spelling mistake: "configurarion" -> "configuration" clk: cdce925: remove redundant check for non-null parent_name clk: versatile: Improve sizeof() usage clk: versatile: Delete error messages for failed memory allocations clk: ux500: Improve sizeof() usage clk: ux500: Delete error messages for failed memory allocations clk: spear: Delete error messages for failed memory allocations clk: ti: Delete error messages for failed memory allocations clk: mmp: Adjust checks for NULL pointers ...
| * clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen2017-11-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Below is the call trace of tegra210_init_pllu() function: start_kernel() -> time_init() --> of_clk_init() ---> tegra210_clock_init() ----> tegra210_pll_init() -----> tegra210_init_pllu() Because the preemption is disabled in the start_kernel before calling time_init, tegra210_init_pllu is actually in an atomic context while it includes a readl_relaxed_poll_timeout that might sleep. So this patch just changes this readl_relaxed_poll_timeout() to its atomic version. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen2017-11-013-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both tegra124-dfll and clk-dfll are using platform_set_drvdata to set drvdata of the exact same pdev while they use different pointers for the drvdata. Once the drvdata has been overwritten by tegra124-dfll, clk-dfll will never get its td pointer as it expects. Since tegra124-dfll merely needs its soc pointer in its remove function, this patch fixes the bug by removing the overwriting in the tegra124-dfll file and letting the tegra_dfll_unregister return an soc pointer for it. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix cclk_lp divisor registerMichał Mirosław2017-11-011-1/+1
| | | | | | | | | | | | | | | | | | | | According to comments in code and common sense, cclk_lp uses its own divisor, not cclk_g's. Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30") Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko2017-11-011-1/+1
| | | | | | | | | | | | | | | | | | AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko2017-11-011-5/+1
| | | | | | | | | | | | | | | | | | The APBDMA clock is defined in the common clock gates table that is used by Tegra30+. Tegra20 can use it too, let's remove the custom definition and use the common one. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko2017-11-011-1/+1
| | | | | | | | | | | | | | | | APBDMA represents a clock gate to the APB DMA controller, the actual clock source for the controller is PCLK. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-11 19:15:57 +0000