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| * | | clk: meson-gxbb: un-export the CPU clockMartin Blumenstingl2017-05-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU clock defined in the Meson GX clock driver is actually a left-over from the Meson8b clock controller. Un-export the clock so we can remove it from the driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| * | | clk: meson-gxbb: expose UART clocksHelmut Klein2017-05-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose the clock ids of the three none AO uarts to the dt-bindings Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy the commit message to match similar change] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| * | | clk: meson-gxbb: expose SPICC gateNeil Armstrong2017-05-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose the SPICC gate clock to enable the SPICC controller. Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy commit message to match similar changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| * | | clk: meson-gxbb: expose spdif master clockJerome Brunet2017-05-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose the spdif master clock and the mux to select the appropriate spdif clock parent depending on the data source. Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| * | | clk: meson-gxbb: expose i2s master clockJerome Brunet2017-05-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose cts_amclk in the device tree bindings Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| * | | clk: meson-gxbb: expose spdif clock gatesJerome Brunet2017-05-291-2/+2
| |/ / | | | | | | | | | | | | | | | | | | Expose the clock gates required for the spdif output Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* | | clk: palmas: undo preparation of a clock source.Arvind Yadav2017-06-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Undo preparation of a clock source, if palmas_clks_init_configure is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | Merge tag 'clk-renesas-for-v4.13-tag1' of ↵Michael Turquette2017-06-0214-72/+1319
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next clk: renesas: Updates for v4.13 - Add more module clocks for R-Car H3 ES2.0 and M3-W, - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support for module resets, which are not supported by the existing driver, - Rework Kconfig and Makefile logic, - Small fixes and cleanups.
| * | | clk: renesas: r8a7794: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-245-2/+266
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7792: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-245-2/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-245-2/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7790: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-245-1/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: Rework Kconfig and Makefile logicGeert Uytterhoeven2017-05-244-37/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC (which may change in the future), - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies. This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol CLK_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/clk/renesas/ during the build. Note that currently not all (sub)drivers are enabled for compile-testing, as they depend on independent fixes in other subsystems. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: renesas: cpg-mssr: Initialize error pointer using ERR_PTR()Geert Uytterhoeven2017-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coccinelle warns: drivers/clk/renesas/renesas-cpg-mssr.c:323:14-21: ERROR: PTR_ERR applied after initialization to constant on line 260 Initialize clk using ERR_PTR(-ENOTSUPP) instead of NULL to fix this. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0Geert Uytterhoeven2017-05-151-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cfr. the errata of April 14, 2017, for the R-Car Gen3 Hardware Manual Rev. 0.53E. These have no user-visible effect, as the clock frequencies stay the same. Fixes: 5573d194128b4733 ("clk: renesas: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | | clk: renesas: Use pm_clk_no_clocks() helper i.s.o. direct accessGeert Uytterhoeven2017-05-152-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm_subsys_data.clock_list member exists only if CONFIG_PM_CLK=y. Hence direct accesses to this field break compile-testing on platforms where CONFIG_PM_CLK=n. To fix this, use the pm_clk_no_clocks() helper instead, for which a dummy version is provided if CONFIG_PM_CLK=n. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <simon.horman@netronome.com>
| * | | clk: renesas: Do not build clk-div6 for R8A7792Geert Uytterhoeven2017-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car V2H does not have "DIV6" programmable clocks, hence there is no need to build clk-div6.o. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | | clk: renesas: r8a7796: Add INTC-EX clockTakeshi Kihara2017-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the "intc-ex" clock to the R8A7796 CPG MSSR driver. According to information from the hardware team the INTC-EX parent clock is CP. The next data sheet version will include this information. [takeshi.kihara.df: Ported from commit f099aa075749 ("clk: shmobile: r8a7795: Add INTC-EX clock") to drivers/clk/renesas/r8a7796-cpg-mssr.c] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add PCIe clocksHarunobu Kurokawa2017-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds PCIEC{0,1} clocks for R8A7796 SoC. Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add PWM clockRyo Kodama2017-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds PWM clock for PWM. Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Correct parent clock] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add HS-USB clockKazuya Mizuguchi2017-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds HS-USB-IF clock for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add Sound DVC clocksKazuya Mizuguchi2017-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds adds SCU(DVC{0,1}) clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add Sound SRC clockKazuya Mizuguchi2017-05-151-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SCU(all), SCU(SRC{0,1,2,3,4,5,6,7,8,9}), SCU(CTU00, CTU01, CTU02, CTU03, MIX0) and SCU (CTU10, CTU11, CTU12, CTU13, MIX1) clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add Sound SSI clockKazuya Mizuguchi2017-05-151-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SSI(all) and SSI{0,1,2,3,4,5,6,7,8,9} clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add USB-DMAC clocksHiromitsu Yamasaki2017-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB-DMAC{0,1} clocks for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add Audio-DMAC clocksHiromitsu Yamasaki2017-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds A-DMAC{0,1} clocks for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Correct parent clocks, preserve sort order] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add EHCI/OHCI clocksKazuya Mizuguchi2017-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7796: Add HDMI clockKoji Matsuoka2017-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds HDMI-IF0 clock for R8A7796 SoC. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7795: Add HS-USB ch3 clockTakeshi Kihara2017-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds valid HS-USB ch3 clock from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7795: Add USB-DMAC ch3 clockTakeshi Kihara2017-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports the clock of USB-DMAC ch3 module added from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7795: Add EHCI/OHCI ch3 clockTakeshi Kihara2017-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports the clock of EHCI/OHCI ch3 module added from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7745: Remove PLL configs for MD19=0Geert Uytterhoeven2017-05-151-11/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's Manual Rev.1.00, MD19=0 is a prohibited setting. Hence stop looking at MD19, and remove all PLL configurations for MD19=0. Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocksGeert Uytterhoeven2017-05-151-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RZ/G1E does not have the SCU-SRC[0789] modules and module clocks. Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2Geert Uytterhoeven2017-05-151-4/+19
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car V2H and E2 do not have the PLL0CR register, but use a fixed multiplier (depending on mode pins) and divider. This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on R-Car V2H and E2 from 1.5 GHz to 1 GHz. Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G Clock Pulse Generator support core. Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Fixes: 0dce5454d5c25858 ("ARM: shmobile: Initial r8a7794 SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | | clk: Fix __set_clk_rates error print-stringBryan O'Donoghue2017-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When failing to set a clock the printout emitted is incorrect. "u32 rate" is formatted as %d and should be %u whereas "unsigned long clk_set_rate()" is formatted as %ld and should be %lu as per Documentation/printk-formats.txt. Fixes: 2885c3b2a3da ("clk: Show correct information when fail to set clock rate") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | clk: scpi: fix return type of __scpi_dvfs_round_rateSudeep Holla2017-06-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The frequencies above the maximum value of signed integer(i.e. 2^31 -1) will overflow with the current code. This patch fixes the return type of __scpi_dvfs_round_rate from 'int' to 'unsigned long'. Fixes: cd52c2a4b5c4 ("clk: add support for clocks provided by SCP(System Control Processor)") Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | clk: qoriq: Separate root input clock for core PLLs on ls1012aScott Wood2017-06-011-14/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ls1012a has separate input root clocks for core PLLs versus the platform PLL, with the latter described as sysclk in the hw docs. If a second input clock, named "coreclk", is present, this clock will be used for the core PLLs. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | clk: at91: fix clk-generated parentingAlexandre Belloni2017-06-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_generated_startup is called after clk_hw_register. So the first call to get_parent will not have the correct value (i.e. 0) and because this is cached, it may never be updated. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Fixes: df70aeef6083 ("clk: at91: add generated clock driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | clk: imx7d: Fix the powerdown bit location of PLL DDRFabio Estevam2017-06-013-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to the MX7D Reference Manual the powerdown bit of CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | clk: mvebu: armada-38x: add support for 1866MHz variantsRalph Sennhauser2017-06-011-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the list of supported CPU frequencies. Also update multiplier and divisor for the l2clk and ddrclk. Noticed by the following warning: [ 0.000000] Selected CPU frequency (16) unsupported Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | Merge branch 'clk-ap806' into clk-nextMichael Turquette2017-06-011-36/+71
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| * | clk: mvebu: ap806: introduce a new bindingGregory CLEMENT2017-06-011-12/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As for cp110, the initial intent when the binding of the ap806 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/cc8c8c40fa4c4e71133033358992ec38e5aa2be5.1496239589.git-series.gregory.clement@free-electrons.com
| * | clk: mvebu: ap806: do not depend anymore of the *-clock-output-namesGregory CLEMENT2017-06-011-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As it was done for the cp110, this patch modifies the way the clock names are created. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/e66cdd54d36c6bef78460a51e577f171b6ccb031.1496239589.git-series.gregory.clement@free-electrons.com
| * | clk: mvebu: ap806: cosmetic improvementGregory CLEMENT2017-06-011-7/+8
| |/ | | | | | | | | | | | | | | | | Instead of using &pdev->dev all over the place, introduce a pointer variable for it. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/5a55e081d96fc6d2a28331b59df90f56d32a9f24.1496239589.git-series.gregory.clement@free-electrons.com
* | Merge tag 'meson-clk-fixes-for-4.12-rc2' of ↵Michael Turquette2017-05-251-0/+1
|\ \ | | | | | | | | | | | | | | | | | | git://github.com/baylibre/clk-meson into clk-fixes KConfig fix: - clk: meson: gxbb: fix build error without RESET_CONTROLLER
| * | clk: meson: gxbb: fix build error without RESET_CONTROLLERTobias Regnery2017-05-161-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With CONFIG_RESET_CONTROLLER=n we see the following link error in the meson gxbb clk driver: drivers/built-in.o: In function 'gxbb_aoclkc_probe': drivers/clk/meson/gxbb-aoclk.c:161: undefined reference to 'devm_reset_controller_register' Fix this by selecting the reset controller subsystem. Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver") Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: Added fixes-by tag] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* / clk: sunxi-ng: sun5i: Fix ahb_bist_clk definitionBoris Brezillon2017-05-251-1/+1
|/ | | | | | | | | | | | | | | | | | | | AHB BIST gate is actually controlled with bit 7. This bug was detected while trying to use the NAND controller which is using the DMA engine to transfer data to the NAND. Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit, the core was disabling the DMA engine clock as part of its 'disable unused clks' procedure, which was causing all DMA transfers to fail after this point. Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver") Cc: stable@vger.kernel.org Reported-by: Angus Ainslie <angus@akkea.ca> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1495643669-28221-1-git-send-email-boris.brezillon@free-electrons.com
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-05-10107-1313/+5162
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Sort of on the quieter side this time, which is probably due more to me not catching up as quickly on patch review than anything else. Overall it seems normal though, a few small changes to the core, mostly small non-critical fixes here and there as well as driver updates for new and existing hardware support. The biggest things are the TI clk driver rework to lay the groundwork for clkctrl support in the next merge window and the AmLogic audio/graphics clk support. Core: - clk_possible_parents debugfs file so we know which parents a clk could possibly have - Fix to make clk rate change notifiers stop on the first failure instead of continuing New Drivers: - Mediatek MT6797 SoCs - hi655x PMIC clks - AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks - Allwinner H5 SoCs and PRCM hardware Updates: - Nvidia Tegra T210 cleanups and non-critical fixes - TI OMAP cleanups in preparation for clkctrl support - trivial fixes like kcalloc(), devm_* conversions, and seq_puts() - ZTE zx296718 SoC VGA clks - Rockchip clk-ids, fixups, and rename of rk1108 to rv1108 - IDT VersaClock 5P49V5935 support - Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits) clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL clk: ti: divider: try to fix ti_clk_register_divider clk: mvebu: Use kcalloc() in two functions clk: mvebu: Use kcalloc() in of_cpu_clk_setup() clk: nomadik: Delete error messages for a failed memory allocation in two functions clk: nomadik: Use seq_puts() in nomadik_src_clk_show() clk: Improve a size determination in two functions clk: Replace four seq_printf() calls by seq_putc() clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe() clk: si5351: Use devm_kcalloc() in si5351_i2c_probe() clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics() reset: mediatek: Add MT2701 ethsys reset controller include file clk: mediatek: add mt2701 ethernet reset clk: hi6220: Add the hi655x's pmic clock clk: ti: fix building without legacy omap3 clk: ti: fix linker error with !SOC_OMAP4 clk: hi3620: Fix a typo in one variable name clk: hi3620: Delete error messages for a failed memory allocation in two functions clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init() clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init() ...
| * clk: x86: pmc-atom: Checking for IS_ERR() instead of NULLDan Carpenter2017-05-011-2/+2
| | | | | | | | | | | | | | | | | | | | clkdev_hw_create() returns NULLs on error, it doesn't return error pointers. Fixes: 41ee7caf59e1 ("clk: x86: add "mclk" alias for Baytrail/Cherrytrail") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: ti: divider: try to fix ti_clk_register_dividerArnd Bergmann2017-04-281-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6c0afb503937 ("clk: ti: convert to use proper register definition for all accesses") converted all register accesses in the TI clk driver to use a proper struct instead of a void pointer casted struct that fits into a u32. Unfortunately, it missed a conversion here in the didivder code, leading to a compiler warning like so: drivers/clk/ti/divider.c: In function 'ti_clk_register_divider': drivers/clk/ti/divider.c:460:8: error: 'reg' may be used uninitialized in this function [-Werror=maybe-uninitialized] Treating a 'u32' variable as a structure leads to a stack overflow here, and the register address we pass down is never initialized. Convert this part of the code as well so things work properly. Fixes: 6c0afb503937 ("clk: ti: convert to use proper register definition for all accesses") Signed-off-by: Arnd Bergmann <arnd@arndb.de> [sboyd@codeaurora.org: Fixed fixes tag, rewrote commit message, s/reg_setup/reg/] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 22:44:01 +0000