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path: root/drivers/clk
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* clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycleMarek Szyprowski2017-10-041-0/+15
* Merge tag 'v4.14-rockchip-clkfixes-1' of git://git.kernel.org/pub/scm/linux/k...Stephen Boyd2017-09-291-5/+7
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| * clk: rockchip: add sclk_timer5 as critical clock on rk3128Elaine Zhang2017-09-171-0/+1
| * clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs errorElaine Zhang2017-09-171-4/+4
| * clk: rockchip: add pclk_pmu as critical clock on rk3128Elaine Zhang2017-09-171-1/+2
* | clk: Export clk_bulk_prepare()Bjorn Andersson2017-09-291-0/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2017-09-13114-1037/+8040
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| * clk: si5351: fix PLL resetRussell King2017-09-011-7/+5
| * clk: at91: clk-generated: make gclk determine audio_pll rateQuentin Schulz2017-09-011-6/+57
| * clk: at91: clk-generated: create function to find best_diffQuentin Schulz2017-09-011-14/+27
| * clk: at91: add audio pll clock driversQuentin Schulz2017-09-012-0/+537
| * clk: at91: clk-generated: remove useless divisor loopQuentin Schulz2017-09-011-13/+12
| * clk: mb86s7x: Drop non-building driverAndreas Färber2017-09-012-391/+0
| * clk: ti: check for null return in strrchr to avoid null dereferencingColin Ian King2017-08-311-1/+1
| * clk: Don't write error code into divider registerAlex Frid2017-08-311-2/+4
| * clk: uniphier: add video input subsystem clockKatsuhiro Suzuki2017-08-311-0/+6
| * clk: uniphier: add audio system clockKatsuhiro Suzuki2017-08-311-0/+12
| * clk: stm32h7: Add stm32h743 clock driverGabriel Fernandez2017-08-312-0/+1411
| * clk: gate: expose clk_gate_ops::is_enabledGabriel Fernandez2017-08-311-1/+2
| * clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()Gabriel Fernandez2017-08-311-6/+6
| * clk: uniphier: add PXs3 clock dataMasahiro Yamada2017-08-313-0/+43
| * clk: hi6220: change watchdog clock sourceLeo Yan2017-08-311-3/+3
| * clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808Elaine Zhang2017-08-311-2/+2
| * clk: cs2000: Add cs2000_set_saved_rateGaku Inami2017-08-311-4/+10
| * clk: imx51: propagate rate across ipu_di*_selLucas Stach2017-08-311-4/+4
| * Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd2017-08-314-0/+1531
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| | * clk: sunxi-ng: Add sun4i/sun7i CCU driverPriit Laes2017-08-244-0/+1531
| * | clk: sunxi: fix uninitialized accessArnd Bergmann2017-08-301-0/+4
| * | clk: versatile: make clk_ops constBhumika Goyal2017-08-301-1/+1
| * | ARC: clk: introduce HSDK pll driverEugeniy Paltsev2017-08-303-0/+439
| * | clk: zte: constify clk_div_tableArvind Yadav2017-08-301-3/+3
| * | clk: imx: constify clk_div_tableArvind Yadav2017-08-305-12/+12
| * | clk: uniphier: add ethernet clock control supportKunihiko Hayashi2017-08-301-0/+10
| * | clk: gemini: hands off PCI OE bitLinus Walleij2017-08-301-7/+0
| * | clk: ux500: prcc: constify clk_ops.Arvind Yadav2017-08-301-3/+3
| * | clk: ux500: sysctrl: constify clk_ops.Arvind Yadav2017-08-301-4/+4
| * | clk: ux500: prcmu: constify clk_ops.Arvind Yadav2017-08-301-7/+7
| * | clk: msm8996-gcc: add missing smmu clksSrinivas Kandagatla2017-08-231-0/+28
| * | clk: tegra: Fix Tegra210 PLLU initializationAlex Frid2017-08-231-2/+4
| * | clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid2017-08-231-3/+3
| * | clk: tegra: Fix T210 PLLRE registrationAlex Frid2017-08-231-20/+1
| * | clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid2017-08-231-39/+9
| * | clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-234-49/+10
| * | clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver2017-08-231-2/+4
| * | clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver2017-08-231-1/+1
| * | clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid2017-08-231-1/+2
| * | clk: tegra: Fix T210 effective NDIV calculationAlex Frid2017-08-231-4/+5
| * | clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver2017-08-231-0/+2
| * | clk: tegra210: remove non-existing VFIR clockPeter De Schrijver2017-08-231-1/+0
| * | clk: tegra: disable SSC for PLL_D2Peter De Schrijver2017-08-231-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 21:29:10 +0000