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* Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson i...Stephen Boyd2018-05-012-4/+3
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| * clk: meson: meson8b: fix meson8b_cpu_clk parent clock nameMartin Blumenstingl2018-04-251-1/+2
| * clk: meson: meson8b: fix meson8b_fclk_div3_div clock nameMartin Blumenstingl2018-04-251-1/+1
| * clk: meson: drop meson_aoclk_gate_regmap_opsYixun Lan2018-04-251-2/+0
* | clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmapJerome Brunet2018-04-161-1/+10
* | clk: honor CLK_MUX_ROUND_CLOSEST in generic clk muxJerome Brunet2018-04-162-4/+13
* | clk: cs2000: mark resume function as __maybe_unusedArnd Bergmann2018-04-161-1/+1
* | Merge branch 'clk-stm32mp1' into clk-fixesStephen Boyd2018-04-161-31/+23
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| * clk: stm32mp1: remove ck_apb_dbg clockGabriel Fernandez2018-04-061-4/+0
| * clk: stm32mp1: set stgen_k clock as criticalGabriel Fernandez2018-04-061-2/+1
| * clk: stm32mp1: add missing tzc2 clockGabriel Fernandez2018-04-061-3/+6
| * clk: stm32mp1: fix SAI3 & SAI4 clocksGabriel Fernandez2018-04-061-2/+2
| * clk: stm32mp1: remove unused dfsdm_src[] constGabriel Fernandez2018-04-061-4/+0
| * clk: stm32mp1: add missing staticGabriel Fernandez2018-04-061-16/+14
* | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-04-13158-3894/+14649
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| * \ Merge branch 'clk-davinci' into clk-nextStephen Boyd2018-04-062-0/+8
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| | * | clk: davinci: add a reset lookup table for psc0Bartosz Golaszewski2018-04-062-0/+8
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| *-------. \ \ Merge branches 'clk-stratix10', 'clk-imx', 'clk-bcm', 'clk-cs2000' and 'clk-i...Stephen Boyd2018-04-0618-70/+1299
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| | | | | | * | | clk: imx: add clock driver for imx6sllBai Ping2018-04-062-0/+341
| | | | | | * | | clk: imx: add new gate/gate2 wrapper funtionBai Ping2018-04-061-0/+14
| | | | | | * | | clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy muxBai Ping2018-04-061-2/+2
| | | | | * | | | clk: cs2000: set pm_ops in hibernate-compatible wayNikita Yushchenko2018-04-061-1/+1
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| | | | * / / / clk: bcm2835: De-assert/assert PLL reset signal when appropriateBoris Brezillon2018-04-061-3/+5
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| | | * | | | clk: imx7d: Move clks_init_on before any clock operationsDong Aisheng2018-04-061-7/+7
| | | * | | | clk: imx7d: Correct ahb clk parent selectAnson Huang2018-04-061-1/+1
| | | * | | | clk: imx7d: Correct dram pll typeAnson Huang2018-04-061-1/+3
| | | * | | | clk: imx7d: Add USB clock informationPeter Chen2018-04-061-1/+8
| | | * | | | clk: imx: pllv2: avoid using uninitialized valuesLucas Stach2018-03-161-1/+5
| | | * | | | Merge tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd2018-03-143-48/+55
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| | | | * | | | clk: imx6ull: Add epdc_podf instead of sim_podfLeonard Crestez2018-03-131-1/+4
| | | | * | | | clk: imx: imx7d: correct video pll clock treeAnson Huang2018-03-011-40/+44
| | | | * | | | clk: imx: imx6sx: update cko mux optionsAnson Huang2018-02-221-7/+7
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| | * | / / / clk: socfpga: stratix10: add clock driver for Stratix10 platformDinh Nguyen2018-04-068-5/+854
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| *-------. \ \ \ \ Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and...Stephen Boyd2018-04-0629-45/+4394
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| | | | | | * | | | clk: ti: fix flag space conflict with clkctrl clocksTero Kristo2018-04-051-4/+5
| | | | | * | | | | clk: uniphier: add additional ethernet clock lines for Pro4Kunihiko Hayashi2018-04-051-0/+3
| | | | | * | | | | clk: uniphier: add SATA clock control supportKunihiko Hayashi2018-04-051-0/+6
| | | | | * | | | | clk: uniphier: add PCIe clock control supportKunihiko Hayashi2018-04-051-0/+3
| | | | | * | | | | clk: uniphier: add ethernet clock control support for PXs3Kunihiko Hayashi2018-03-231-0/+2
| | | | | * | | | | clk: uniphier: add Pro4/Pro5/PXs2 audio system clockKatsuhiro Suzuki2018-03-191-0/+11
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| | | | * | | | | clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399Lin Huang2018-03-231-2/+2
| | | | * | | | | clk: rockchip: Fix error return in phase clock registrationShawn Lin2018-03-231-2/+4
| | | | * | | | | clk: rockchip: Correct the behaviour of restoring cached phaseShawn Lin2018-03-231-2/+14
| | | | * | | | | clk: rockchip: Fix wrong parents for MMC phase clock for rk3328Shawn Lin2018-03-231-8/+8
| | | | * | | | | clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228Shawn Lin2018-03-231-1/+1
| | | | * | | | | clk: rockchip: Add 1.6GHz PLL rate for rk3399Derek Basehore2018-03-141-0/+1
| | | | * | | | | clk: rockchip: Restore the clock phase after the rate was changedShawn Lin2018-03-131-1/+38
| | | | * | | | | clk: rockchip: Prevent calculating mmc phase if clock rate is zeroShawn Lin2018-03-051-0/+23
| | | | * | | | | clk: rockchip: Free the memory on the error pathShawn Lin2018-03-021-4/+18
| | | | * | | | | clk: rockchip: add flags for rk3328 dclk_lcdcZheng Yang2018-02-121-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 06:44:54 +0000