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* Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2014-03-081-2/+34
|\ | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clk driver fix from Mike Turquette: "Single fix for a clock driver merged in 3.14-rc1. Without this fix the CPU frequency cannot be scaled" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change
| * clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency changeBenoit Cousson2014-03-051-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Z clock frequency change is effective only after setting the kick bit located in the FRQCRB register. Without that, the CA15 CPUs clock rate will never change. Fix that by checking if the kick bit is cleared and enable it to make the clock rate change effective. The bit is cleared automatically upon completion. Signed-off-by: Benoit Cousson <bcousson+renesas@baylibre.com> Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk:at91: Fix memory leak in of_at91_clk_master_setup()Masanari Iida2014-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | cppcheck detected following error [clk-master.c:245]: (error) Memory leak: characteristics The original code forgot to free characteristics when irq_of_parse_and_map() failed. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: nomadik: fix multiplatform problemLinus Walleij2014-02-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Nomadik debugfs screws up multiplatform boots if debugfs is enabled on the multiplatform image, since it's a simple initcall that is unconditionally executed and reads from certain memory locations. Fix this by checking that the driver has been properly initialized, so a base offset to the Nomadik SRC controller exists, before proceeding to register debugfs files. Reported-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: Correct handling of NULL clk in __clk_{get, put}Sylwester Nawrocki2014-02-241-6/+7
| | | | | | | | | | | | | | | | Ensure clk->kref is dereferenced only when clk is not NULL. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge branch 'clk-tegra-more-fixes-3.14' of ↵Mike Turquette2014-02-247-31/+45
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes Fixes stray access to undefined registers, use of wrong clock parents & running clocks at wrong rates. All of these issues cause regressions in the form of boards that are unable to boot or crash and die horrible deaths.
| * | clk: tegra124: remove gr2d and gr3d clocksPeter De Schrijver2014-02-201-2/+0
| | | | | | | | | | | | | | | | | | | | | Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the vic03 and gpu clocks respectively. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * | clk: tegra: Fix vic03 mux indexPeter De Schrijver2014-02-201-3/+1
| | | | | | | | | | | | | | | | | | The vic03 mux uses a linear mapping. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| * | clk: tegra: use max divider if divider overflowsAndrew Bresticker2014-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When requesting a rate less than the minimum clock rate for a divider, use the maximum divider value instead of bailing out with an error. This matches the behavior of the generic clock divider. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
| * | clk: tegra: cclk_lp has a pllx/2 dividerAndrew Bresticker2014-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
| * | clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker2014-02-174-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
| * | clk: tegra: fix host1x clock on Tegra124Mark Zhang2014-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents. Change thte id to tegra_clk_host1x_8 so that the correct clock gets registered. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
| * | clk: tegra: PLLD2 fixes for hdmiDavid Ung2014-02-171-8/+7
| | | | | | | | | | | | | | | | | | | | | Set correct pll_d2_out0 divider and correct the p div values for pll_d2. Signed-off-by: David Ung <davidu@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
| * | clk: tegra: Fix PLLD mnp tableRhyland Klein2014-02-171-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
| * | clk: tegra: Fix PLLP rate tableGabe Black2014-02-171-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | This table had settings for 216MHz, but PLLP is (and is supposed to be) configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is not set, the kernel will panic in clk_pll_recalc_rate(). Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
| * | clk: tegra: Correct clock number for UARTEThierry Reding2014-02-171-1/+1
| | | | | | | | | | | | | | | | | | UARTE has clock number 66. Number 65 is the right one for UARTD. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: Add missing Tegra20 fuse clksPeter De Schrijver2014-02-171-0/+2
| |/ | | | | | | | | | | | | Add clocks required for accessing fuses on Tegra20. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'for_3.14-rcx/clk-fixes' of ↵Mike Turquette2014-02-181-0/+1
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into clk-fixes
| * | clk: keystone: gate: fix clk_init_data initializationIvan Khoronzhuk2014-02-101-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clk_init_data struct is allocated in the stack. All members of this struct should be initialized before using otherwise it will lead to unpredictable situation as it can contain garbage. Ultimately the clk->flag field contains garbage. In my case it leads that flag CLK_IGNORE_UNUSED is set for most of clocks. As result a bunch of unused clocks cannot be disabled. So initialize flags in this structure too. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | Merge tag 'mvebu-clk-fixes-3.14' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2014-02-184-50/+44
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-fixes mvebu clock fixes for v3.14 - kirkwood, dove, armada-xp, armada-370 - force clock init order broken by sorting DT ocp nodes by address - fixes boot failures on affected platforms
| * | clk: mvebu: kirkwood: maintain clock init orderSebastian Hesselbarth2014-02-061-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | clk: mvebu: dove: maintain clock init orderSebastian Hesselbarth2014-02-061-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | clk: mvebu: armada-xp: maintain clock init orderSebastian Hesselbarth2014-02-061-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | clk: mvebu: armada-370: maintain clock init orderSebastian Hesselbarth2014-02-061-11/+10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Init order of CLK_OF_DECLARE'd drivers depends on compile order. Unfortunately, clk_of_init does not allow drivers to return errors, e.g. -EPROBE_DEFER if parent clocks have not been registered, yet. To avoid init order woes for MVEBU clock drivers, we take care of proper init order ourselves. This patch joins core-clk and gating-clk init to maintain proper init order. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | clk: shmobile: rcar-gen2: Fix qspi divisorLaurent Pinchart2014-02-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocksLaurent Pinchart2014-02-181-1/+9
|/ | | | | | | | | | | The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'clk-for-linus-3.14-part2' of ↵Linus Torvalds2014-01-2825-67/+4268
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull more clock framework changes from Mike Turquette: "The second half of the clock framework pull requeust for 3.14 is dominated by platform support for Qualcomm's MSM SoCs, DT binding updates for TI's OMAP-ish processors and additional support for Samsung chips. Additionally there are other smaller clock driver changes and several last minute fixes. This pull request also includes the HiSilicon support that depends on the already-merged arm-soc pull request" [ Fix up stupid compile error in the source tree with evil merge - Grumpy Linus ] * tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux: (49 commits) clk: sort Makefile clk: sunxi: fix overflow when setting up divided factors clk: Export more clk-provider functions dt-bindings: qcom: Fix warning with duplicate dt define clk: si5351: remove variant from platform_data clk: samsung: Remove unneeded semicolon clk: qcom: Fix modular build ARM: OMAP3: use DT clock init if DT data is available ARM: AM33xx: remove old clock data and link in new clock init code ARM: AM43xx: Enable clock init ARM: OMAP: DRA7: Enable clock init ARM: OMAP4: remove old clock data and link in new clock init code ARM: OMAP2+: io: use new clock init API ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT ARM: OMAP3: hwmod: initialize clkdm from clkdm_name ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm ARM: OMAP2+: clock: use driver API instead of direct memory read/write ARM: OMAP2+: clock: add support for indexed memmaps ARM: dts: am43xx clock data ARM: dts: AM35xx: use DT clock data ...
| * clk: sort MakefileMike Turquette2014-01-271-39/+37
| | | | | | | | Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: fix overflow when setting up divided factorsEmilio López2014-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | Currently, we are allocating space for two pointers, when we actually may need to store three of them (two divisors plus the original clock). Fix this, and change sizeof(type) to sizeof(*var) to keep checkpatch.pl happy. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Export more clk-provider functionsStephen Boyd2014-01-271-0/+7
| | | | | | | | | | | | | | | | | | Allow drivers to be compiled as modules by exporting more clock provider functions. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: si5351: remove variant from platform_dataSebastian Hesselbarth2014-01-272-16/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9807362bfe1748d9bb48eecb9261f1b1aaafea1c "clk: si5351: declare all device IDs for module loading" removed the common i2c_device_id and introduced new ones for each variant of the clock generator. Instead of exploiting that information in the driver, it still depends on platform_data passing the chips .variant. This removes the now redundant .variant from the platform_data and puts it in i2c_device_id's .driver_data instead. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: Remove unneeded semicolonSachin Kamat2014-01-171-1/+1
| | | | | | | | | | | | | | Semicolon not needed after switch statement. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: qcom: Fix modular buildStephen Boyd2014-01-171-6/+6
| | | | | | | | | | | | | | | | | | | | According to Documentation/kbuild/makefiles.txt these symbols should be clk-qcom-y. Otherwise the build will fail if CONFIG_COMMON_CLK_QCOM=m. Fix it. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add am43xx clock init fileTero Kristo2014-01-172-0/+119
| | | | | | | | | | | | | | | | | | | | clk-43xx.c now contains the clock init functionality for am43xx, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add omap3 clock init fileTero Kristo2014-01-172-1/+402
| | | | | | | | | | | | | | | | | | | | clk-3xxx.c now contains the clock init functionality for omap3, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add interface clock support for OMAP3Tero Kristo2014-01-172-0/+126
| | | | | | | | | | | | | | | | | | | | OMAP3 has interface clocks in addition to functional clocks, which require special handling for the autoidle and idle status register offsets mainly. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add am33xx clock init fileTero Kristo2014-01-172-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | clk-33xx.c now contains the clock init functionality for am33xx, including DT clock registration and adding of static clkdev entries. This patch also moves the omap2_clk_enable_init_clocks declaration to the driver include, as this is needed by the am33xx clock init code. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add dra7 clock init fileTero Kristo2014-01-172-0/+333
| | | | | | | | | | | | | | | | | | | | clk-7xx.c now contains the clock init functionality for dra7, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: DRA7: Add APLL supportJ Keerthy2014-01-172-1/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: omap5: Initialize USB_DPLL at bootRoger Quadros2014-01-171-1/+17
| | | | | | | | | | | | | | | | | | | | | | USB_DPLL must be initialized and locked at boot so that USB modules can work. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add omap5 clock init fileTero Kristo2014-01-172-0/+240
| | | | | | | | | | | | | | | | | | | | clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add omap4 clock init fileTero Kristo2014-01-172-0/+317
| | | | | | | | | | | | | | | | | | | | clk-44xx.c now contains the clock init functionality for omap4, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: ti: add support for basic mux clockTero Kristo2014-01-173-2/+248
| | | | | | | | | | | | | | | | | | ti,mux-clock provides now a binding for basic mux support. This is just using the basic clock type. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add support for clockdomain bindingTero Kristo2014-01-172-1/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some OMAP clocks require knowledge about their parent clockdomain for book keeping purposes. This patch creates a new DT binding for TI clockdomains, which act as a collection of device clocks. Clockdomain itself is rather misleading name for the hardware functionality, as at least on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either clocks and/or IP blocks, thus idle-domain or such might be more appropriate. For most cases on these SoCs, the kernel doesn't even need the information and the mappings can be ignored. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add support for gate clockTero Kristo2014-01-172-1/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for TI specific gate clocks. These behave as basic gate-clock, but have different ops / hw-ops for controlling the actual gate, for example waiting until the clock is ready. Several sub-types are supported: - ti,gate-clock: basic gate clock with default ops/hwops - ti,clkdm-gate-clock: clockdomain level gate control - ti,dss-gate-clock: gate clock with DSS specific hardware handling - ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling - ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: ti: add support for TI fixed factor clockTero Kristo2014-01-172-1/+68
| | | | | | | | | | | | | | | | | | This behaves exactly in similar manner to basic fixed-factor-clock, but adds a few properties on top for handling clock hardware autoidling. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: ti: add support for ti divider-clockTero Kristo2014-01-173-2/+489
| | | | | | | | | | | | | | | | | | This patch adds support for TI divider clock binding, which simply uses the basic clock divider to provide the features needed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: ti: add composite clock supportTero Kristo2014-01-172-1/+270
| | | | | | | | | | | | | | | | | | | | This is a multipurpose clock node, which contains support for multiple sub-clocks. Uses basic composite clock type to implement the actual functionality, and TI specific gate, mux and divider clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: add autoidle supportTero Kristo2014-01-172-1/+134
| | | | | | | | | | | | | | | | | | | | | | TI clk driver now routes some of the basic clocks through own registration routine to allow autoidle support. This routine just checks a couple of device node properties and adds autoidle support if required, and just passes the registration forward to basic clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * CLK: TI: Add DPLL clock supportTero Kristo2014-01-172-0/+559
| | | | | | | | | | | | | | | | | | The OMAP clock driver now supports DPLL clock type. This patch also adds support for DT DPLL nodes. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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