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| | | | * | | clk: rockchip: rk3368: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2a19c3cc-5f4d-4d03-90b2-e0bb13b0502f@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | | | * | | clk: rockchip: rk3328: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/38ea6be0-3596-49ec-8de9-aef9c7f2bbb6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | | | * | | clk: rockchip: rk3308: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/9fbca2d8-f904-4913-ba05-8715e748a454@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | | | * | | clk: rockchip: rk3288: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/af141286-7994-4e3f-93e2-6ee4e718ef8a@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | | | * | | clk: rockchip: rk3228: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2ee6f0a5-a1bb-4b62-ae6b-8f3828f8eccc@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | | | * | | clk: rockchip: rk3036: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/c8e73847-f472-4473-ac55-068cb28b98f6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | | | * | | clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker2024-08-281-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/5ad12808-61f5-4e3b-801e-85231375b6a6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | | | * | | clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228Jonas Karlman2024-07-291-1/+1
| | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically parented by the hdmiphy clk and it is expected that the DCLK_VOP and hdmiphy clk rate are kept in sync. Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used on RK3328, to make full use of all possible supported display modes. Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP") Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20240615170417.3134517-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | | * | | clk: samsung: add top clock support for ExynosAuto v920 SoCSunyeal Hong2024-08-232-0/+1174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block and they will generate bus clocks. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-5-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | | * | | clk: samsung: clk-pll: Add support for pll_531xSunyeal Hong2024-08-232-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pll531x PLL is used in Exynos Auto v920 SoC for shared pll. pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120 MHz) PLL531x FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL FOUT = (MDIV + F/2^32-F[31]) x FIN/(PDIV x 2^SDIV) for fractional PLL Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-4-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | | * | | clk: samsung: exynos7885: Add USB related clocks to CMU_FSYSDavid Virag2024-08-211-14/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in theory supports USB3 SuperSpeed, but is only used as USB2 in all known devices. These clocks are needed for everything related to USB. While at it, also remove the CLK_SET_RATE_PARENT capability of CLK_MOUT_FSYS_USB30DRD_USER, since it's not actually needed. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240816175034.769628-3-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | | * | | clk: samsung: clk-pll: Add support for pll_1418xDavid Virag2024-08-212-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pll1418x is used in Exynos7885 SoC for USB PHY clock. Operation-wise it is very similar to pll0822x, except that MDIV is only 9 bits wide instead of 10, and we use the CON1 register in the PLL macro's "con" parameter instead of CON3 like this: PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB, pll_usb_rate_table), Technically the PLL should work fine with pll0822x code if the PLL tables are correct, but it's more "correct" to actually update the mask. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240816175034.769628-2-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | | * | | clk: samsung: exynosautov9: add dpum clock supportKwanghoon Son2024-08-111-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dpum clock for exynosautov9. Signed-off-by: Kwanghoon Son <k.son@samsung.com> Link: https://lore.kernel.org/r/20240809-clk_dpum-v3-3-359decc30fe2@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | | * | | clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOPDavid Virag2024-08-081-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Exynos7885 (and seemingly all modern Exynos SoCs) all PLLs have a MUX attached to them controlled by bit 4 in the PLL's CON0 register. These MUXes can select between OSCCLK or the PLL's output, essentially making the PLL bypassable. These weren't modeled in the driver because the vendor provided drivers didn't model it properly, instead setting them when updating the PMS values. Not having them modeled didn't cause any problems in this case, since these MUXes were set to the PLL's output by default, but this is not the case everywhere in this SoC. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240806121157.479212-6-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | | * | | clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fixDavid Virag2024-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update CLKS_NR_FSYS to the proper value after a fix in DT bindings. This should always be the last clock in a CMU + 1. Fixes: cd268e309c29 ("dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS") Cc: stable@vger.kernel.org Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240806121157.479212-5-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | | * | | clk: samsung: exynos850: Add TMU clockSam Protsenko2024-07-311-1/+6
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TMU PCLK clock in CMU_PERI unit. It acts simultaneously as an interface clock (to access TMU registers) and an operating clock which makes TMU IP-core functional. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240723163311.28654-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * / / clk: provide devm_clk_get_optional_enabled_with_rate()Bartosz Golaszewski2024-09-051-0/+28
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are clock users in the kernel that can't use devm_clk_get_optional_enabled() as they need to set rate after getting the clock and before enabling it. Provide a managed helper that wraps these operations in the correct order. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240805-clk-new-helper-v2-1-e5fdd1e1d729@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *---. \ \ Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-nextStephen Boyd2024-09-2149-129/+1372
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-amlogic: clk: meson: introduce symbol namespace for amlogic clocks clk: meson: axg-audio: add sm1 earcrx clocks clk: meson: axg-audio: setup regmap max_register based on the SoC dt-bindings: clock: axg-audio: add earcrx clock ids clk: meson: s4: pll: Constify struct regmap_config clk: meson: s4: peripherals: Constify struct regmap_config clk: meson: c3: pll: Constify struct regmap_config clk: meson: c3: peripherals: Constify struct regmap_config clk: meson: a1: pll: Constify struct regmap_config clk: meson: a1: peripherals: Constify struct regmap_config * clk-microchip: clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs clk: at91: sam9x7: add sam9x7 pmc driver dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT clk: at91: sama7g5: move mux table macros to header file clk: at91: sam9x7: add support for HW PLL freq dividers clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7 * clk-imx: (27 commits) clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL clk: imx95: enable the clock of NETCMIX block control dt-bindings: clock: add RMII clock selection dt-bindings: clock: add i.MX95 NETCMIX block control clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit ...
| | | | * \ \ Merge branch 'clk-imx-old' into clk-imxStephen Boyd2024-09-0514-50/+192
| | | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-imx: (22 commits) clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit clk: imx: composite-93: keep root clock on when mcore enabled clk: imx: composite-8m: Enable gate clk with mcore_booted clk: imx: imx6ul: fix default parent for enet*_ref_sel clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks ...
| | | | | * | | clk: imx: composite-7ulp: Use NULL instead of 0Peng Fan2024-06-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Address the sparse warnings " sparse warnings: (new ones prefixed by >>) >> drivers/clk/imx/clk-composite-7ulp.c:85:24: sparse: sparse: Using plain integer as NULL pointer " Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406220536.JnAncjqz-lkp@intel.com/ Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240624024351.488492-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: add missing MODULE_DESCRIPTION() macrosJeff Johnson2024-06-242-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/mxc-clk.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/clk-imxrt1050.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240602-md-clk-imx-v1-1-5c6d240f6fab@quicinc.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rateMarek Vasut2024-06-212-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The media_disp[12]_pix clock supply LCDIFv3 pixel clock output. These clocks are usually the only downstream clock from Video PLL on i.MX8MP. Allow these clocks to reconfigure the Video PLL, as that results in accurate pixel clock. If the Video PLL is not reconfigured, the pixel clock accuracy is low. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240531202648.277078-1-marex@denx.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: fracn-gppll: update rate tablePeng Fan2024-06-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add 1039.5MHz clock for video PLL to fulfill the LVDS display 148.5MHz * 7 requirement - Add 800MHz clock for ARM PLL Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-16-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: imx8qxp: Parent should be initialized earlier than the clockPeng Fan2024-06-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-15-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clkPeng Fan2024-06-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: 91e916771de0 ("clk: imx: scu: remove legacy scu clock binding support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-14-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocksOliver F. Brown2024-06-211-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPI Pixel and PHY Reference can use the bypass clock as a source. The MIPI bypass clock is the Pixel clock from the Display controller via the pixel link. Using the pixel clock for the PHY reference allows the MIPI bit clock match the pixel rate exactly. The MIPI pixel clock is currently set to be source from the bypass clock in the SCFW. This patch allows the pixel clock parent to be set by the kernel in the event that the SCFW default clock parent may change in the future. Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com> Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-13-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: imx8qxp: Add LVDS bypass clocksPeng Fan2024-06-211-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS clocks with imx_clk_scu2 as the parent needs to explicitly set. In order to make sure MIPI DSI works well after suspend/resume, the LVDS pixel and phy clocks must be initialized before the MIPI tx_esacpe and rx_escape clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all on the same MSLICE. They all share the same clock parent. So, setting the parent source or rate affects all of these clocks. In the LVDS use case the MIPI tx_escape and rx_escape are not saved and restored. So, LVDS works for either clock initialization order. For MIPI case, LVDS must be initialized first. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-12-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical oneJacky Bai2024-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-11-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: imx8mn: add sai7_ipg_clk clock settingsAdrian Alonso2024-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IMX8MN_CLK_SAI7_IPG clock entry. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-10-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7DPeng Fan2024-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add flag 'CLK_SET_RATE_PARENT' to 'IMX7D_LCDIF_PIXEL_ROOT_SRC' to propagate rate changes from LCDIF pixel clock to video PLL to provide more accurate clock rate for LCDIF pixel clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-9-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7DPeng Fan2024-06-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For i.MX7D DRAM related mux clock, the clock source change should ONLY be done done in low level asm code without accessing DRAM, and then calling clk API to sync the HW clock status with clk tree, it should never touch real clock source switch via clk API, so CLK_SET_PARENT_GATE flag should NOT be added, otherwise, DRAM's clock parent will be disabled when DRAM is active, and system will hang. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: imx8mp: fix clock tree update of TF-A managed clocksZhipeng Wang2024-06-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. since commit 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: clk_set_parent(dram_apb_src, sys1_pll_40m);(busfreq-imx8mq.c) commit 926bf91248dd ("clk: imx8m: fix clock tree update of TF-A managed clocks") adds this method and enables 8mm, 8mn and 8mq. i.MX8MP also needs it. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Another reason to this patch is that powersave image BT music requires dram to be 400MTS, so clk_set_parent(dram_alt_src, sys1_pll_800m); is required. Without this patch, it will not succeed. Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Zhipeng Wang <zhipeng.wang_1@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-7-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: fracn-gppll: fix fractional part of PLL getting lostPengfei Li2024-06-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fractional part of PLL gets lost after re-enabling the PLL. the MFN can NOT be automatically loaded when doing frac PLL enable/disable, So when re-enable PLL, configure mfn explicitly. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: composite-7ulp: Check the PCC present bitYe Li2024-06-211-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When some module is disabled by fuse, its PCC PR bit is default 0 and PCC is not operational. Any write to this PCC will cause SError. Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp") Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: composite-93: keep root clock on when mcore enabledJacky Bai2024-06-211-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we assumed that the root clock slice is enabled by default when kernel boot up. But the bootloader may disable the clocks before jump into kernel. The gate ops should be registered rather than NULL to make sure the disabled clock can be enabled when kernel boot up. Refine the code to skip disable the clock if mcore booted. Fixes: a740d7350ff7 ("clk: imx: imx93: add mcore_booted module paratemter") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Tested-by: Chancel Liu <chancel.liu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: composite-8m: Enable gate clk with mcore_bootedPeng Fan2024-06-211-11/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bootloader might disable some CCM ROOT Slices. So if mcore_booted set with display CCM ROOT disabled by Bootloader, kernel display BLK CTRL driver imx8m_blk_ctrl_driver_init may hang the system because the BUS clk is disabled. Add back gate ops, but with disable doing nothing, then the CCM ROOT will be enabled when used. Fixes: bb7e897b002a ("clk: imx8m: check mcore_booted before register clk") Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240607133347.3291040-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: imx6ul: fix default parent for enet*_ref_selSebastien Laveze2024-06-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clk_set_parent for "enet1_ref_sel" and "enet2_ref_sel" are incorrect, therefore the original requirements to have "enet_clk_ref" as output sourced by iMX ENET PLL as a default config is not met. Only "enet[1,2]_ref_125m" "enet[1,2]_ref_pad" are possible parents for "enet1_ref_sel" and "enet2_ref_sel". This was observed as a regression using a custom device tree which was expecting this default config. This can be fixed at the device tree level but having a default config matching the original behavior (before refclock mux) will avoid breaking existing configs. Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") Link: https://lore.kernel.org/lkml/20230306020226.GC143566@dragon/T/ Signed-off-by: Sebastien Laveze <slaveze@smartandconnective.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/20240528151434.227602-1-slaveze@smartandconnective.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpllShengjiu Wang2024-06-211-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Reference Manual of i.MX8MP The parent clock of "earc_phy" is "sai_pll_out_div2", The parent clock of "audpll" is "osc_24m". Add CLK_GATE_PARENT() macro for usage of specifying parent clock. Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1718350923-21392-6-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocksShengjiu Wang2024-06-211-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CLK_SET_RATE_PARENT flags that when the device driver sets the child clock rate, parent clock frequency can be refined accordingly. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1718350923-21392-5-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | | * | | clk: imx: clk-audiomix: Add reset controllerShengjiu Wang2024-06-212-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Audiomix block control can be a reset controller for Enhanced Audio Return Channel (EARC), which is one of modules in this audiomix subsystem. The reset controller is supported by the auxiliary device framework. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.kernel.org/r/1718350923-21392-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | * | | | clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SELMichel Alex2024-09-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add ethernet refclock mux support") sets the internal clock as default ethernet clock. Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct parent and shall be used instead. Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M is the correct parent. Cc: stable@vger.kernel.org Signed-off-by: Alex Michel <alex.michel@wiedemann-group.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | * | | | clk: imx95: enable the clock of NETCMIX block controlWei Fang2024-08-291-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NETCMIX block control consists of registers for configuration of peripherals in the NETC domain, so enable the clock of NETCMIX to support the configuration. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240829011849.364987-4-wei.fang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | | * | | | clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_dataShengjiu Wang2024-08-291-9/+29
| | | | | |/ / | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM driver, but they are the parent clocks for other clocks, in order to use assigned-clock-parents in device tree, the ".fw_name" can't be used, need to assign the clk_hw pointer for the imx8qm_mclk_sels[], imx8qxp_mclk_sels[], imx8dxl_mclk_sels[]. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1720600860-18866-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | | * | | | clk: at91: sama7g5: Allocate only the needed amount of memory for PLLsClaudiu Beznea2024-08-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The maximum number of PLL components on SAMA7G5 is 3 (one fractional part and 2 dividers). Allocate the needed amount of memory for sama7g5_plls 2d array. Previous code used to allocate 7 array entries for each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which parses the sama7g5_plls 2d array. Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5") Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240714141315.19480-1-claudiu.beznea@tuxon.dev Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| | | * | | | clk: at91: sam9x7: add sam9x7 pmc driverVarshini Rajendran2024-08-072-0/+947
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the PMC clocks of sam9x7 Soc family. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Link: https://lore.kernel.org/r/20240729070811.1990964-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| | | * | | | clk: at91: sama7g5: move mux table macros to header fileVarshini Rajendran2024-08-072-25/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the mux table init and fill macro function definitions from the sama7g5 pmc driver to the pmc.h header file since they will be used by other SoC's pmc drivers as well like sam9x7. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20240729070753.1990866-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| | | * | | | clk: at91: sam9x7: add support for HW PLL freq dividersVarshini Rajendran2024-08-072-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and 4 respectively, both have a hardware divider /2. This has to be taken into account in the software to obtain the right frequencies. Support for the same is added in the PLL driver. fcorepllack -----> HW Div = 2 -+--> fpllack | +--> HW Div = 2 ---> fplladiv2ck In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz after the hardware divider and the plladiv2 freq is 400 MHz after the hardware divider (given that the DIVPMC is 0). Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20240729070746.1990805-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| | | * | | | clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputsVarshini Rajendran2024-08-074-6/+21
| | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAM9X7 SoC family supports different core output frequencies for different PLL IDs. To handle the same in the PLL driver, a separate parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers are aligned to the PLL driver by adding the core output freq range in the PLL characteristics configurations. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20240729070737.1990756-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| | * | | | clk: meson: introduce symbol namespace for amlogic clocksJerome Brunet2024-07-2925-25/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Symbols exported by the Amlogic clock modules are only meant to be used by Amlogic clock controller drivers. Using a dedicated symbols namespace make that clear and help clean the global namespace of symbols other modules do no need. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240719094228.3985595-1-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | clk: meson: axg-audio: add sm1 earcrx clocksJerome Brunet2024-07-292-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CMDC, DMAC and peripheral clocks for the eARC RX device found on the sm1 SoC family Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240719093934.3985139-4-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-23 13:21:05 +0000