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* Merge tag 'sunxi-clk-fixes-for-5.18-2' of ↵Stephen Boyd2022-04-252-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull Allwinner clk fixes from Jernej Skrabec: - Add missing sentinel - check return value for platform_get_resource() - mark rtc-32k as critical * tag 'sunxi-clk-fixes-for-5.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi: sun9i-mmc: check return value after calling platform_get_resource() clk: sunxi-ng: sun6i-rtc: Mark rtc-32k as critical clk: sunxi-ng: fix not NULL terminated coccicheck error
| * clk: sunxi: sun9i-mmc: check return value after calling platform_get_resource()Yang Yingliang2022-04-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | It will cause null-ptr-deref if platform_get_resource() returns NULL, we need check the return value. Fixes: 7a6fca879f59 ("clk: sunxi: Add driver for A80 MMC config clocks/resets") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220421134308.2885094-1-yangyingliang@huawei.com
| * clk: sunxi-ng: sun6i-rtc: Mark rtc-32k as criticalSamuel Holland2022-04-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because some newer hardware variants have multiple possible parents for the RTC's timekeeping clock, this driver models it as a "rtc-32k" clock. However, it does not add any consumer for this clock. This causes the common clock framework to disable it, preventing RTC time access. Since the RTC's timekeeping clock should always be enabled, regardless of which drivers are loaded, let's mark this clock as critical instead of adding a consumer in the RTC driver. Fixes: d91612d7f01a ("clk: sunxi-ng: Add support for the sun6i RTC clocks") Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220411050100.40964-1-samuel@sholland.org
| * clk: sunxi-ng: fix not NULL terminated coccicheck errorWan Jiabing2022-04-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following coccicheck error: ./drivers/clk/sunxi-ng/ccu-sun6i-rtc.c:348:1-2: sun6i_rtc_ccu_match is not NULL terminated at line 348 Fixes: d91612d7f01a ("clk: sunxi-ng: Add support for the sun6i RTC clocks") Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220328073931.36544-1-wanjiabing@vivo.com
* | clk: microchip: mpfs: add RTCREF clock controlConor Dooley2022-04-221-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | The reference clock used by the PolarFire SoC's onboard rtc was missing from the clock driver. Add this clock at the "config" clock level, with the external reference clock as its parent. Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-9-conor.dooley@microchip.com Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: microchip: mpfs: re-parent the configurable clocksConor Dooley2022-04-221-19/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the mpfs clock driver uses a reference clock called the "msspll", set in the device tree, as the parent for the cpu/axi/ahb (config) clocks. The frequency of the msspll is determined by the FPGA bitstream & the bootloader configures the clock to match the bitstream. The real reference is provided by a 100 or 125 MHz off chip oscillator. However, the msspll clock is not actually the parent of all clocks on the system - the reference clock for the rtc/mtimer actually has the off chip oscillator as its parent. In order to fix this, add support for reading the configuration of the msspll & reparent the "config" clocks so that they are derived from this clock rather than the reference in the device tree. Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-8-conor.dooley@microchip.com Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: microchip: mpfs: mark CLK_ATHENA as criticalConor Dooley2022-04-221-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | CLK_ATHENA is another fabric interconnect and should be marked as critical as with FIC0-3, since disabling it will cause part of the fabric to go into reset. Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-3-conor.dooley@microchip.com Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: microchip: mpfs: fix parents for FIC clocksConor Dooley2022-04-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | The fabric interconnects are on the AXI bus not AHB. Update their parent clocks to fix this. Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-2-conor.dooley@microchip.com Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: clk-rcg2: fix gfx3d frequency calculationDmitry Baryshkov2022-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the commit 948fb0969eae ("clk: Always clamp the rounded rate"), the clk_core_determine_round_nolock() would clamp the requested rate between min and max rates from the rate request. Normally these fields would be filled by clk_core_get_boundaries() called from clk_round_rate(). However clk_gfx3d_determine_rate() uses a manually crafted rate request, which did not have these fields filled. Thus the requested frequency would be clamped to 0, resulting in weird frequencies being requested from the hardware. Fix this by filling min_rate and max_rate to the values valid for the respective PLLs (0 and ULONG_MAX). Fixes: 948fb0969eae ("clk: Always clamp the rounded rate") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220419235447.1586192-1-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reported-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: microchip: mpfs: don't reset disabled peripheralsConor Dooley2022-04-211-4/+0
|/ | | | | | | | | | | | | | | | | | The current clock driver for PolarFire SoC puts the hardware behind "periph" clocks into reset if their clock is disabled. CONFIG_PM was recently added to the riscv defconfig and exposed issues caused by this behaviour, where the Cadence GEM was being put into reset between its bringup & the PHY bringup: https://lore.kernel.org/linux-riscv/9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com/ Fix this (for now) by removing the reset from mpfs_periph_clk_disable. Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220411072340.740981-1-conor.dooley@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2022-04-032-136/+14
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fix from Stephen Boyd: "A single revert to fix a boot regression seen when clk_put() started dropping rate range requests. It's best to keep various systems booting so we'll kick this out and try again next time" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: Revert "clk: Drop the rate range on clk_put()"
| * Revert "clk: Drop the rate range on clk_put()"Stephen Boyd2022-04-022-136/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7dabfa2bc4803eed83d6f22bd6f045495f40636b. There are multiple reports that this breaks boot on various systems. The common theme is that orphan clks are having rates set on them when that isn't expected. Let's revert it out for now so that -rc1 boots. Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Reported-by: Tony Lindgren <tony@atomide.com> Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org> Link: https://lore.kernel.org/r/366a0232-bb4a-c357-6aa8-636e398e05eb@samsung.com Cc: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220403022818.39572-1-sboyd@kernel.org
* | Merge tag 'rtc-5.18' of ↵Linus Torvalds2022-04-016-0/+425
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux Pull RTC updates from Alexandre Belloni: "The bulk of the patches are about replacing the uie_unsupported struct rtc_device member by a feature bit. Subsystem: - remove uie_unsupported, all users have been converted to clear RTC_FEATURE_UPDATE_INTERRUPT and provide a reason - RTCs with an alarm with a resolution of a minute are now letting the core handle rounding down the alarm time - fix use-after-free on device removal New driver: - OP-TEE RTC PTA Drivers: - sun6i: Add H616 support - cmos: Fix the AltCentury for AMD platforms - spear: set range" * tag 'rtc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (56 commits) rtc: check if __rtc_read_time was successful rtc: gamecube: Fix refcount leak in gamecube_rtc_read_offset_from_sram rtc: mc146818-lib: Fix the AltCentury for AMD platforms rtc: optee: add RTC driver for OP-TEE RTC PTA rtc: pm8xxx: Return -ENODEV if set_time disallowed rtc: pm8xxx: Attach wake irq to device clk: sunxi-ng: sun6i-rtc: include clk/sunxi-ng.h rtc: remove uie_unsupported rtc: xgene: stop using uie_unsupported rtc: hym8563: switch to RTC_FEATURE_UPDATE_INTERRUPT rtc: hym8563: let the core handle the alarm resolution rtc: hym8563: switch to devm_rtc_allocate_device rtc: efi: switch to RTC_FEATURE_UPDATE_INTERRUPT rtc: efi: switch to devm_rtc_allocate_device rtc: add new RTC_FEATURE_ALARM_WAKEUP_ONLY feature rtc: spear: fix spear_rtc_read_time rtc: spear: drop uie_unsupported rtc: spear: set range rtc: spear: switch to devm_rtc_allocate_device rtc: pcf8563: switch to RTC_FEATURE_UPDATE_INTERRUPT ...
| * | clk: sunxi-ng: sun6i-rtc: include clk/sunxi-ng.hAlexandre Belloni2022-03-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This solves: >> drivers/clk/sunxi-ng/ccu-sun6i-rtc.c:334:5: warning: no previous prototype for 'sun6i_rtc_ccu_probe' [-Wmissing-prototypes] 334 | int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg) | ^~~~~~~~~~~~~~~~~~~ Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220320210905.6606-1-alexandre.belloni@bootlin.com
| * | clk: sunxi-ng: sun6i-rtc: Add support for H6Samuel Holland2022-03-231-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H6 supports IOSC calibration and an ext-osc32k input. Unlike newer SoCs, it has a single parent for its fanout clock. Add support for H6 in the CCU driver, replacing the support in the existing early OF clock provider. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20220203021736.13434-7-samuel@sholland.org
| * | clk: sunxi-ng: Add support for the sun6i RTC clocksSamuel Holland2022-03-234-0/+400
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTC power domain in sun6i and newer SoCs manages the 16 MHz RC oscillator (called "IOSC" or "osc16M") and the optional 32 kHz crystal oscillator (called "LOSC" or "osc32k"). Starting with the H6, this power domain also handles the 24 MHz DCXO (called variously "HOSC", "dcxo24M", or "osc24M") as well. The H6 also adds a calibration circuit for IOSC. Later SoCs introduce further variations on the design: - H616 adds an additional mux for the 32 kHz fanout source. - R329 adds an additional mux for the RTC timekeeping clock, a clock for the SPI bus between power domains inside the RTC, and removes the IOSC calibration functionality. Take advantage of the CCU framework to handle this increased complexity. This driver is intended to be a drop-in replacement for the existing RTC clock provider. So some runtime adjustment of the clock parents is needed, both to handle hardware differences, and to support the old binding which omitted some of the input clocks. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20220203021736.13434-6-samuel@sholland.org
| * | clk: sunxi-ng: mux: Allow muxes to have keysSamuel Holland2022-03-232-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The muxes in the RTC can only be updated when setting a key field to a specific value. Add a feature flag to denote muxes with this property. Since so far the key value is always the same, it does not need to be provided separately for each mux. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20220203021736.13434-5-samuel@sholland.org
* | | Merge tag 'clk-for-linus' of ↵Linus Torvalds2022-03-30194-3662/+10765
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's one large change in the core clk framework here. We change how clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate dt-bindings: clock: drop useless consumer example dt-bindings: clock: renesas: Make example 'clocks' parsable clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() clk: visconti: prevent array overflow in visconti_clk_register_gates() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments ...
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| *-. \ Merge branches 'clk-sifive' and 'clk-visconti' into clk-nextStephen Boyd2022-03-299-239/+219
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-sifive: clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being * clk-visconti: clk: visconti: prevent array overflow in visconti_clk_register_gates()
| | | * | clk: visconti: prevent array overflow in visconti_clk_register_gates()Dan Carpenter2022-03-173-2/+5
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code was using -1 to represent that there was no reset function. Unfortunately, the -1 was stored in u8 so the if (clks[i].rs_id >= 0) condition was always true. This lead to an out of bounds access in visconti_clk_register_gates(). Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220316083533.GA30941@kili Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | clk: sifive: Move all stuff into SoCs header files from C filesZong Li2022-03-156-235/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve PRCI driver to reduce the complexity, we remove the SoCs C files by putting all stuff in each SoCs header files, and include these SoCs-specific header files in core of PRCI. It can also avoid the W=1 kernel build warnings about variable defined but not used [-Wunused-const-variable=], like commit 487dc7bb6a0c ("clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used") does. Signed-off-by: Zong Li <zong.li@sifive.com> Suggested-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Lee Jones <lee.jones@linaro.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/a3c7ec5c46c1d8be455d1c347db4855bb56cec53.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | clk: sifive: Add SoCs prefix in each SoCs-dependent dataZong Li2022-03-152-50/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is prerequisite for moving SoCs C files into SoCs header files. Currently, fu540-prci.c and fu740-prci.c use same names for several macro definitions and variables, it would cause redefinition error when we trying to include all stuff in sifive-prci.c. In this patch, we also remove the temporary macro definitions which are added by previous patch. Signed-off-by: Zong Li <zong.li@sifive.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/7728ef662c59449ce954b1b62c6ad5241e07adfb.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | clk: sifive: duplicate the macro definitions for the time beingZong Li2022-03-152-2/+15
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a temporary patch in whole patch set. We are going to change the macro name in dt-binding, in order to avoid breaking the driver build and git bisect, add these macro definitions for the time being, and we will remove them later. Signed-off-by: Zong Li <zong.li@sifive.com> Link: https://lore.kernel.org/r/8cfd57f01cfb59adb716eb13ca0c8250c246dcb2.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *-----. \ Merge branches 'clk-range', 'clk-uniphier', 'clk-apple' and 'clk-qcom' into ↵Stephen Boyd2022-03-2929-945/+5927
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range - Support for NCO blocks on Apple SoCs * clk-range: clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate clk: bcm: rpi: Run some clocks at the minimum rate allowed clk: bcm: rpi: Set a default minimum rate clk: bcm: rpi: Add variant structure clk: Add clk_drop_range clk: Always set the rate on clk_set_range_rate clk: Use clamp instead of open-coding our own clk: Always clamp the rounded rate clk: Enforce that disjoints limits are invalid clk: Introduce Kunit Tests for the framework clk: Fix clk_hw_get_clk() when dev is NULL * clk-uniphier: clk: uniphier: Fix fixed-rate initialization * clk-apple: clk: clk-apple-nco: Allow and fix module building MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE clk: clk-apple-nco: Add driver for Apple NCO dt-bindings: clock: Add Apple NCO * clk-qcom: (61 commits) clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops ...
| | | | | * | clk: qcom: gcc-msm8994: Fix gpll4 widthKonrad Dybcio2022-03-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpll4 postdiv is actually a div4, so make sure that Linux is aware of this. This fixes the following error messages: mmc1: Card appears overclocked; req 200000000 Hz, actual 343999999 Hz mmc1: Card appears overclocked; req 400000000 Hz, actual 687999999 Hz Fixes: aec89f78cf01 ("clk: qcom: Add support for msm8994 global clock controller") Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220319174940.341137-1-konrad.dybcio@somainline.org Tested-by: Petr Vorel <petr.vorel@gmail.com> Reviewed-by: Petr Vorel <petr.vorel@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | * | clk: qcom: Add display clock controller driver for SM6125Martin Botka2022-03-093-0/+719
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the display clock controller found on SM6125 based devices. This allows display drivers to probe and control their clocks. Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303131812.302302-4-marijn.suijten@somainline.org
| | | | | * | clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and KconfigMarijn Suijten2022-03-092-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to keep at least the list of `CONFIG_SM_` drivers sorted alphabetically, SDX_GCC_65 should have been moved one line up. This in turn makes it easier and cleaner to add the followup SM_DISPCC_6125 driver in the right place, right before SM_DISPCC_8250. Fixes: d79afa201328 ("clk: qcom: Add SDX65 GCC support") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303131812.302302-2-marijn.suijten@somainline.org
| | | | | * | clk: qcom: gcc: Add emac GDSC support for SM8150Bhupesh Sharma2022-03-091-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the EMAC GDSC defines and driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303084824.284946-4-bhupesh.sharma@linaro.org
| | | | | * | clk: qcom: gcc: sm8150: Fix some identation issuesBhupesh Sharma2022-03-091-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix identation issues with usb30 gdsc structs in gcc-sm8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303084824.284946-3-bhupesh.sharma@linaro.org
| | | | | * | clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150Bhupesh Sharma2022-03-091-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the UFS_CARD and UFS_PHY GDSC defines & driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303082140.240745-2-bhupesh.sharma@linaro.org
| | | | | * | clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150Bhupesh Sharma2022-03-091-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302203045.184500-4-bhupesh.sharma@linaro.org
| | | | | * | clk: qcom: clk-rcg2: Update the frac table for pixel clockTaniya Das2022-03-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support the new numerator and denominator for pixel clock on SM8350 and support rgb101010, RGB888 use cases on SM8450. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220227175536.3131-2-tdas@codeaurora.org
| | | | | * | clk: qcom: clk-rcg2: Update logic to calculate D value for RCGTaniya Das2022-03-091-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The display pixel clock has a requirement on certain newer platforms to support M/N as (2/3) and the final D value calculated results in underflow errors. As the current implementation does not check for D value is within the accepted range for a given M & N value. Update the logic to calculate the final D value based on the range. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org
| | | | | * | clk: qcom: smd: Add missing MSM8998 RPM clocksKonrad Dybcio2022-03-091-13/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing RPM-provided clocks on msm8998 and reorder the definitions where needed. Tested-by: Jami Kettunen <jami.kettunen@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226214126.21209-3-konrad.dybcio@somainline.org
| | | | | * | clk: qcom: smd: Add missing RPM clocks for msm8992/4Konrad Dybcio2022-03-091-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XO and MSS_CFG were omitted when first adding the clocks for these SoCs. Add them, and while at it, move the XO clock to the top of the definition list, as ideally everyone should start using it sooner or later.. Fixes: b4297844995f ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks") Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226214126.21209-2-konrad.dybcio@somainline.org
| | | | | * | clk: qcom: gcc-ipq806x: add CryptoEngine resetsAnsuel Smith2022-03-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing CryptoEngine resets. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-15-ansuelsmth@gmail.com
| | | | | * | clk: qcom: gcc-ipq806x: add CryptoEngine clocksAnsuel Smith2022-03-081-0/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com
| | | | | * | clk: qcom: gcc-ipq806x: add additional freq for sdc tableAnsuel Smith2022-03-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add additional freq supported for the sdc table. The ops are changed to the floor_ops to handle a freq request of 52kHz where we need to provide a freq of 51.2kHz instead for stability reason. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com
| | | | | * | clk: qcom: clk-rcg: add clk_rcg_floor_ops opsAnsuel Smith2022-03-082-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clk_rcg_floor_ops for clock that can't provide a stable freq and require to use a floor freq to provide the requested frequency. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-10-ansuelsmth@gmail.com
| | | | | * | clk: qcom: gcc-ipq806x: add unusued flag for critical clockAnsuel Smith2022-03-081-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-9-ansuelsmth@gmail.com
| | | | | * | clk: qcom: gcc-ipq806x: add additional freq nss coresAnsuel Smith2022-03-081-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver. Set the freq_tbl for the ubi32_cores to the correct values based on the machine compatible. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com
| | | | | * | clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parentsAnsuel Smith2022-03-081-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com
| | | | | * | clk: qcom: gcc-ipq806x: convert parent_names to parent_dataAnsuel Smith2022-03-081-113/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert parent_names to parent_data to modernize the driver. Where possible use parent_hws directly. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com
| | | | | * | clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0Ansuel Smith2022-03-081-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com
| | | | | * | clk: qcom: Add SDX65 APCS clock controller supportRohit Agarwal2022-03-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update APCS Kconfig to reflect support for SDX65 APCS clock controller. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-6-git-send-email-quic_rohiagar@quicinc.com
| | | | | * | clk: qcom: Add A7 PLL support for SDX65Rohit Agarwal2022-03-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update A7 PLL Kconfig to reflect support for SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-3-git-send-email-quic_rohiagar@quicinc.com
| | | | | * | clk: qcom: Add GPU clock controller driver for SM6350Konrad Dybcio2022-03-083-0/+530
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the GPU clock controller found on SM6350. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-4-konrad.dybcio@somainline.org
| | | | | * | clk: qcom: Add display clock controller driver for SM6350Konrad Dybcio2022-03-083-0/+807
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the display clock controller found on SM6350. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-2-konrad.dybcio@somainline.org
| | | | | * | clk: qcom: rpmhcc: add sc8280xp support to the RPMh clock controllerBjorn Andersson2022-02-241-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Qualcomm SC8280XP platform exposes 5 clocks through the RPMh clock controller. Add these, and the relates active-only variants, to the RPMh clock controller driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220223044516.3776637-2-bjorn.andersson@linaro.org
| | | | | * | clk: qcom: ipq8074: Use floor ops for SDCC1 clockDirk Buchwalder2022-02-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use floor ops on SDCC1 APPS clock in order to round down selected clock frequency and avoid overclocking SD/eMMC cards. For example, currently HS200 cards were failling tuning as they were actually being clocked at 384MHz instead of 192MHz. This caused some boards to disable 1.8V I/O and force the eMMC into the standard HS mode (50MHz) and that appeared to work despite the eMMC being overclocked to 96Mhz in that case. There was a previous commit to use floor ops on SDCC clocks, but it looks to have only covered SDCC2 clock. Fixes: 9607f6224b39 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks") Signed-off-by: Dirk Buchwalder <buchwalder@posteo.de> Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220210173100.505128-1-robimarko@gmail.com
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 06:19:46 +0000