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| | | | | * Merge tag '20220608105238.2973600-1-dmitry.baryshkov@linaro.org' into clk-for...Bjorn Andersson2022-06-255-70/+124
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| | | | | | * clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocksDmitry Baryshkov2022-06-251-34/+15
| | | | | | * clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocksDmitry Baryshkov2022-06-251-36/+13
| | | | | | * clk: qcom: regmap: add PHY clock source implementationDmitry Baryshkov2022-06-253-0/+96
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| | | | | * clk: qcom: mmcc-msm8996: use parent_hws/_data instead of parent_namesDmitry Baryshkov2022-06-251-239/+495
| | | | | * clk: qcom: mmcc-msm8996: move clock parent tables downDmitry Baryshkov2022-06-251-182/+182
| | | | | * clk: qcom: mmcc-msm8996: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov2022-06-251-44/+44
| | | | | * clk: qcom: rpmh: Add note about sleep/wake state for BCMsStephen Boyd2022-06-251-0/+5
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| | | | * clk: imx: clk-fracn-gppll: Add more freq config for video pllPeng Fan2022-06-161-0/+3
| | | | * clk: imx: clk-fracn-gppll: correct rdivPeng Fan2022-06-161-1/+2
| | | | * clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()Liu Ying2022-06-161-11/+13
| | | | * clk: imx: clk-fracn-gppll: fix mfd valuePeng Fan2022-06-161-4/+4
| | | | * clk: imx93: Correct the edma1's parent clockJacky Bai2022-06-161-1/+1
| | | | * clk: imx93: correct nic_media parentPeng Fan2022-06-161-1/+1
| | | | * clk: imx93: use adc_root as the parent clock of adc1Haibo Chen2022-06-161-1/+1
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| | * | clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_configAndi Kleen2022-07-051-1/+1
| | * | clk: renesas: r9a07g043: Add support for RZ/Five SoCLad Prabhakar2022-07-051-0/+32
| | * | clk: renesas: r8a779f0: Add HSCIF clocksWolfram Sang2022-06-171-0/+4
| | * | clk: renesas: r8a779f0: Add PCIe clocksYoshihiro Shimoda2022-06-171-0/+2
| | * | clk: renesas: r8a779f0: Add Z0 and Z1 clock supportGeert Uytterhoeven2022-06-171-0/+2
| | * | clk: renesas: rza1: Remove struct rz_cpgGeert Uytterhoeven2022-06-131-18/+15
| | * | clk: renesas: r8a7779: Remove struct r8a7779_cpgGeert Uytterhoeven2022-06-131-18/+9
| | * | clk: renesas: r8a7778: Remove struct r8a7778_cpgGeert Uytterhoeven2022-06-131-22/+9
| | * | clk: renesas: sh73a0: Remove sh73a0_cpg.regGeert Uytterhoeven2022-06-131-13/+13
| | * | clk: renesas: r8a7740: Remove r8a7740_cpg.regGeert Uytterhoeven2022-06-131-10/+10
| | * | clk: renesas: r8a73a4: Remove r8a73a4_cpg.regGeert Uytterhoeven2022-06-131-11/+11
| | * | clk: renesas: r8a779f0: Add SDHI0 clockWolfram Sang2022-06-131-0/+1
| | * | clk: renesas: r8a779f0: Add thermal clockWolfram Sang2022-06-131-0/+1
| | * | clk: renesas: rzg2l: Fix reset status functionBiju Das2022-06-071-1/+1
| | * | clk: renesas: r9a06g032: Fix UART clkgrp bitselRalph Siemsen2022-06-061-4/+4
| | * | clk: renesas: r9a06g032: Drop some unused fieldsRalph Siemsen2022-06-061-13/+11
| | * | clk: renesas: r9a09g011: Add WDT clock and reset entriesPhil Edworthy2022-06-061-0/+3
| | * | clk: renesas: r9a09g011: Add PFC clock and reset entriesPhil Edworthy2022-06-061-0/+2
| | * | clk: renesas: r9a07g044: Add POEG clock and reset entriesBiju Das2022-06-061-1/+13
| | * | clk: renesas: r9a07g044: Add GPT clock and reset entryBiju Das2022-06-061-1/+4
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| *-----. \ Merge branches 'clk-basic', 'clk-mtk', 'clk-devm-enable' and 'clk-ti-dt' into...Stephen Boyd2022-08-0228-403/+797
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| | | | | * | clk: ti: Stop using legacy clkctrl names for omap4 and 5Tony Lindgren2022-06-163-189/+185
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| | | | * | clk: Remove never used devm_clk_*unregister()Andy Shevchenko2022-06-221-48/+0
| | | | * | clk: Fix pointer casting to prevent oops in devm_clk_release()Uwe Kleine-König2022-06-221-1/+1
| | | | * | clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()Uwe Kleine-König2022-06-151-32/+4
| | | | * | clk: Provide new devm_clk helpers for prepared and enabled clocksUwe Kleine-König2022-06-151-0/+27
| | | | * | clk: generalize devm_clk_get() a bitUwe Kleine-König2022-06-151-17/+49
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| | | * | clk: mediatek: reset: Add infra_ao reset support for MT8186Rex-BC Chen2022-06-151-0/+23
| | | * | clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195Rex-BC Chen2022-06-154-6/+60
| | | * | clk: mediatek: reset: Add reset support for simple probeRex-BC Chen2022-06-152-0/+8
| | | * | clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen2022-06-1513-16/+86
| | | * | clk: mediatek: reset: Change return type for clock reset register functionRex-BC Chen2022-06-152-8/+13
| | | * | clk: mediatek: reset: Support inuput argument index modeRex-BC Chen2022-06-152-1/+25
| | | * | clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen2022-06-1515-43/+85
| | | * | clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen2022-06-1515-40/+186
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