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path: root/drivers/clk
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| | | | * | | | | clk: imx8mq: Unregister clks when of_clk_add_provider failedAnson Huang2019-08-121-1/+9
| | | | * | | | | clk: imx8mm: Unregister clks when of_clk_add_provider failedAnson Huang2019-08-121-1/+6
| | | | * | | | | clk: imx8mq: Mark AHB clock as criticalAbel Vesa2019-08-031-1/+2
| | | | * | | | | clk: imx8mn: Keep uart clocks on for early consoleAnson Huang2019-08-031-0/+10
| | | | * | | | | clk: imx: Remove unused function statementAnson Huang2019-08-031-1/+0
| | | | * | | | | clk: imx7ulp: Make sure earlycon's clock is enabledAnson Huang2019-08-031-0/+31
| | | | * | | | | clk: imx8mm: Switch to platform driverAbel Vesa2019-08-031-21/+36
| | | | * | | | | clk: imx: imx8mm: fix audio pll settingPeng Fan2019-08-031-2/+2
| | | | * | | | | clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80mAnson Huang2019-08-031-1/+1
| | | | * | | | | clk: imx8mm: Fix typo of pwm3 clock's mux option #4Anson Huang2019-08-031-1/+1
| | | | * | | | | clk: imx: Remove unused clk based APIAbel Vesa2019-08-031-24/+0
| | | | * | | | | clk: imx8mq: set correct parent for usb ctrl clocksLi Jun2019-08-031-2/+2
| | | | * | | | | clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOTAnson Huang2019-08-031-1/+1
| | | | * | | | | clk: imx8mm: rename 'share_count_dcss' to 'share_count_disp'Fancy Fang2019-08-031-5/+5
| | | | * | | | | clk: imx8mm: correct the usb1_ctrl parent to be usb_busLi Jun2019-08-031-1/+1
| | | * | | | | | clk: remove extra ---help--- tags in KconfigLubomir Rintel2019-09-171-9/+0
| | | * | | | | | clk: Document of_parse_clkspec() some moreStephen Boyd2019-09-051-6/+37
| | | * | | | | | clk: Remove extraneous 'for' word in commentsRishi Gupta2019-08-171-1/+1
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| | * | | | | | clk: Overwrite clk_hw::init with NULL during clk_register()Stephen Boyd2019-08-161-8/+16
| | * | | | | | clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registeredStephen Boyd2019-08-161-2/+3
| | * | | | | | clk: ti: Don't reference clk_init_data after registrationStephen Boyd2019-08-162-8/+10
| | * | | | | | clk: qcom: Remove error prints from DFS registrationStephen Boyd2019-08-161-7/+1
| | * | | | | | clk: zx296718: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-60/+49
| | * | | | | | clk: milbeaut: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-1/+1
| | * | | | | | clk: socfpga: deindent code to proper indentationStephen Boyd2019-08-161-2/+2
| | * | | | | | clk: sprd: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+3
| | * | | | | | clk: socfpga: Don't reference clk_init_data after registrationStephen Boyd2019-08-162-13/+16
| | * | | | | | clk: sirf: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-4/+8
| | * | | | | | clk: qcom: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+2
| | * | | | | | clk: meson: axg-audio: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+5
| | * | | | | | clk: lochnagar: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-1/+1
| | * | | | | | clk: actions: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+3
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| *-------. \ \ \ \ \ Merge branches 'clk-qcom', 'clk-mtk', 'clk-armada', 'clk-ingenic' and 'clk-me...Stephen Boyd2019-09-1967-1420/+9861
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| | | | | | * | | | | | clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocksNeil Armstrong2019-08-262-1/+61
| | | | | | * | | | | | clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clockNeil Armstrong2019-08-262-1/+198
| | | | | | * | | | | | clk: meson: g12a: add support for SM1 GP1 PLLNeil Armstrong2019-08-262-1/+310
| | | | | | * | | | | | clk: meson: axg-audio: add g12a reset supportJerome Brunet2019-08-202-2/+106
| | | | | * | | | | | | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil2019-08-124-4/+4
| | | | | * | | | | | | clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil2019-08-071-1/+8
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| | | | * | | | | | | clk: mvebu: ap80x: add AP807 clock supportBen Peled2019-09-171-0/+28
| | | | * | | | | | | clk: mvebu: ap806: Prepare the introduction of AP807 clock supportBen Peled2019-09-171-63/+77
| | | | * | | | | | | clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driverOmri Itach2019-09-171-2/+46
| | | | * | | | | | | clk: mvebu: ap806: be more explicit on what SaR isMiquel Raynal2019-09-171-1/+1
| | | | * | | | | | | clk: mvebu: ap80x-cpu: add AP807 CPU clock supportBen Peled2019-09-171-2/+57
| | | | * | | | | | | clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clockChristine Gharzuzi2019-09-171-20/+62
| | | | * | | | | | | clk: mvebu: ap806: Fix clock name for the clusterGregory CLEMENT2019-08-081-2/+2
| | | | * | | | | | | clk: mvebu: add CPU clock driver for Armada 7K/8KGregory CLEMENT2019-08-083-0/+263
| | | | * | | | | | | clk: mvebu: add helper file for Armada AP and CP clocksGregory CLEMENT2019-08-086-42/+61
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| | | * | | | | | | clk: mediatek: Runtime PM support for MT8183 mcucfg clock providerWeiyi Lu2019-09-171-2/+5
| | | * | | | | | | clk: mediatek: Register clock gate with deviceWeiyi Lu2019-09-174-6/+23
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