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* cpufreq: amd-pstate: fix kernel hang issue while amd-pstate unregisteringPerry Yuan2023-01-101-0/+1
| | | | | | | | | | | | | | | | | In the amd_pstate_adjust_perf(), there is one cpufreq_cpu_get() call to increase increments the kobject reference count of policy and make it as busy. Therefore, a corresponding call to cpufreq_cpu_put() is needed to decrement the kobject reference count back, it will resolve the kernel hang issue when unregistering the amd-pstate driver and register the `amd_pstate_epp` driver instance. Fixes: 1d215f0319 ("cpufreq: amd-pstate: Add fast switch function for AMD P-State") Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Tested-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Perry Yuan <perry.yuan@amd.com> Cc: 5.17+ <stable@vger.kernel.org> # 5.17+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* cpufreq: armada-37xx: stop using 0 as NULL pointerMiles Chen2023-01-101-1/+1
| | | | | | | | Use NULL for NULL pointer to fix the following sparse warning: drivers/cpufreq/armada-37xx-cpufreq.c:448:32: sparse: warning: Using plain integer as NULL pointer Signed-off-by: Miles Chen <miles.chen@mediatek.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* cpufreq: apple-soc: Switch to the lowest frequency on suspendHector Martin2023-01-041-0/+2
| | | | | | | | | | Without this, the CPUs are left in a random pstate. Since we don't support deep idle yet (which powers down the CPUs), this results in significantly increased idle power consumption in suspend. Fixes: 6286bbb40576 ("cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states") Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* cpufreq: Add SM6375 to cpufreq-dt-platdev blocklistKonrad Dybcio2023-01-041-0/+1
| | | | | | | | The Qualcomm SM6375 platform uses the qcom-cpufreq-hw driver, so add it to the cpufreq-dt-platdev driver's blocklist. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* cpufreq: Add Tegra234 to cpufreq-dt-platdev blocklistSumit Gupta2022-12-271-0/+1
| | | | | | | | | Tegra234 platform uses the tegra194-cpufreq driver, so add it to the blocklist in cpufreq-dt-platdev driver to avoid the cpufreq driver registration from there. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* cpufreq: qcom-hw: Fix reading "reg" with address/size-cells != 2Konrad Dybcio2022-12-271-2/+20
| | | | | | | | | | | | Commit 054a3ef683a1 ("cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe") assumed that every reg variable is 4*u32 wide (as most new qcom SoCs set #address- and #size-cells to <2>. That is not the case for all of them though. Check the cells values dynamically to ensure the proper region of the DTB is being read. Fixes: 054a3ef683a1 ("cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* cpufreq: CPPC: Add u64 casts to avoid overflowingPierre Gondois2022-12-271-5/+6
| | | | | | | | The fields of the _CPC object are unsigned 32-bits values. To avoid overflows while using _CPC's values, add 'u64' casts. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* cpufreq: apple: remove duplicate intializerArnd Bergmann2022-12-271-1/+0
| | | | | | | | | | | | | | | When -Woverride-init is enabled, gcc notices that the .attr field is initialized twice: drivers/cpufreq/apple-soc-cpufreq.c:331:27: error: initialized field overwritten [-Werror=override-init] 331 | .attr = apple_soc_cpufreq_hw_attr, | ^~~~~~~~~~~~~~~~~~~~~~~~~ Remove the first one, since this is not actually used. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Eric Curtin <ecurtin@redhat.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* Merge tag 'linux-kselftest-next-6.2-rc1' of ↵Linus Torvalds2022-12-121-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest Pull Kselftest updates from Shuah Khan: "Several fixes and enhancements to existing tests and a few new tests: - add new amd-pstate tests and fix and enhance existing ones - add new watchdog tests and enhance existing ones to improve coverage - fixes to ftrace, splice_read, rtc, and efivars tests - fixes to handle egrep obsolescence in the latest grep release - miscellaneous spelling and SPDX fixes" * tag 'linux-kselftest-next-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest: (24 commits) selftests/ftrace: Use long for synthetic event probe test selftests/tpm2: Split async tests call to separate shell script runner selftests: splice_read: Fix sysfs read cases selftests: ftrace: Use "grep -E" instead of "egrep" selftests: gpio: Use "grep -E" instead of "egrep" selftests: kselftest_deps: Use "grep -E" instead of "egrep" selftests/efivarfs: Add checking of the test return value cpufreq: amd-pstate: fix spdxcheck warnings for amd-pstate-ut.c selftests: rtc: skip when RTC is not present selftests/ftrace: event_triggers: wait longer for test_event_enable selftests/vDSO: Add riscv getcpu & gettimeofday test Documentation: amd-pstate: Add tbench and gitsource test introduction selftests: amd-pstate: Trigger gitsource benchmark and test cpus selftests: amd-pstate: Trigger tbench benchmark and test cpus selftests: amd-pstate: Split basic.sh into run.sh and basic.sh. selftests: amd-pstate: Rename amd-pstate-ut.sh to basic.sh. selftests/ftrace: Convert tracer tests to use 'requires' to specify program dependency selftests/ftrace: Add check for ping command for trigger tests selftests/watchdog: Fix spelling mistake "Temeprature" -> "Temperature" selftests/watchdog: add test for WDIOC_GETTEMP ...
| * cpufreq: amd-pstate: fix spdxcheck warnings for amd-pstate-ut.cMeng Li2022-11-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | spdxcheck warnings: (new ones prefixed by >>) >> drivers/cpufreq/amd-pstate-ut.c: 1:28 Invalid License ID: GPL-1.0-or-later drivers/spi/spi-gxp.c: 1:35 Invalid token: =or-later Signed-off-by: Meng Li <li.meng@amd.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
* | cpufreq: stats: Convert to use sysfs_emit_at() APIye xingchen2022-12-061-9/+7
| | | | | | | | | | | | | | | | | | | | Follow the advice of the Documentation/filesystems/sysfs.rst and show() should only use sysfs_emit() or sysfs_emit_at() when formatting the value to be returned to user space. Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | cpufreq: ACPI: Only set boost MSRs on supported CPUsStuart Hayes2022-12-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Stop trying to set boost MSRs on CPUs that don't support boost. This corrects a bug in the recent patch "Defer setting boost MSRs". Fixes: 13fdbc8b8da6 ("cpufreq: ACPI: Defer setting boost MSRs") Signed-off-by: Stuart Hayes <stuart.w.hayes@gmail.com> Reported-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | Merge tag 'cpufreq-arm-updates-6.2' of ↵Rafael J. Wysocki2022-12-068-93/+543
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm Pull cpufreq ARM updates for 6.2 from Viresh Kumar: "- Generalize of_perf_domain_get_sharing_cpumask phandle format (Hector Martin). - New cpufreq driver for Apple SoC CPU P-states (Hector Martin). - Lots of Qualcomm cpufreq driver updates, that include CPU clock provider support, generic cleanups or reorganization, fixed a potential memleak and the return value of cpufreq_driver->get() (Manivannan Sadhasivam, and Chen Hui). - Few updates to Qualcomm cpufreq driver's DT bindings, that include support for CPU clock provider, fixing missing cache related properties, and support for QDU1000/QRU1000 (Manivannan Sadhasivam, Rob Herring, and Melody Olvera). - Add support for ti,am625 SoC and enable build of ti-cpufreq for ARCH_K3 (Dave Gerlach, and Vibhore Vardhan). - tegra186: Use flexible array to simplify memory allocation (Christophe JAILLET)." * tag 'cpufreq-arm-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: dt-bindings: cpufreq: cpufreq-qcom-hw: Add QDU1000/QRU1000 cpufreq cpufreq: tegra186: Use flexible array to simplify memory allocation cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states cpufreq: qcom-hw: Add CPU clock provider support dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider cpufreq: qcom-hw: Fix the frequency returned by cpufreq_driver->get() cpufreq: qcom-hw: Fix memory leak in qcom_cpufreq_hw_read_lut() arm64: dts: ti: k3-am625-sk: Add 1.4GHz OPP cpufreq: ti: Enable ti-cpufreq for ARCH_K3 arm64: dts: ti: k3-am625: Introduce operating-points table cpufreq: dt-platdev: Blacklist ti,am625 SoC cpufreq: ti-cpufreq: Add support for AM625 dt-bindings: cpufreq: qcom: Add missing cache related properties cpufreq: qcom-hw: Move soc_data to struct qcom_cpufreq cpufreq: qcom-hw: Use cached dev pointer in probe() cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe cpufreq: qcom-hw: Remove un-necessary cpumask_empty() check cpufreq: Generalize of_perf_domain_get_sharing_cpumask phandle format
| * | cpufreq: tegra186: Use flexible array to simplify memory allocationChristophe JAILLET2022-12-011-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use flexible array to simplify memory allocation. It saves some memory, avoids an indirection when reading the 'clusters' array and removes some LoC. Detailed explanation: ==================== Knowing that: - each devm_ allocation over-allocates 40 bytes for internal needs - Some rounding is done by the memory allocator on 8, 16, 32, 64, 96, 128, 192, 256, 512, 1024, 2048, 4096, 8192 boundaries and that: - sizeof(struct tegra186_cpufreq_data) = 24 - sizeof(struct tegra186_cpufreq_cluster) = 16 Memory allocations in tegra186_cpufreq_probe() are: data: (24 + 40) = 64 => 64 bytes data->clusters: (2 * 16 + 40) = 72 => 96 bytes So a total of 160 bytes are allocated. 56 for the real need, 80 for internal uses and 24 are wasted. If 'struct tegra186_cpufreq_data' is reordered so that 'clusters' is a flexible array: - it saves one pointer in the structure - only one allocation is needed So, only 96 bytes are allocated: 16 + 2 * 16 + 40 = 88 => 96 bytes Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-statesHector Martin2022-11-304-0/+364
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implements CPU frequency scaling for Apple Silicon SoCs, including M1 (t8103), M1 Max/Pro/Ultra (t600x), and M2 (t8112). Each CPU cluster has its own register set, and frequency management is fully automated by the hardware; the driver only has to write one register. There is boost frequency support, but the hardware will only allow their use if only a subset of cores in a cluster are in non-deep-idle. Since we don't support deep idle yet, these frequencies are not achievable, but the driver supports them. They will remain disabled in the device tree until deep idle is implemented, to avoid confusing users. This driver does not yet implement the memory controller performance state tuning that usually accompanies higher CPU p-states. This will be done in a future patch. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: qcom-hw: Add CPU clock provider supportManivannan Sadhasivam2022-11-241-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qcom CPUFreq hardware (EPSS/OSM) controls clock and voltage to the CPU cores. But this relationship is not represented with the clk framework so far. So, let's make the qcom-cpufreq-hw driver a clock provider. This makes the clock producer/consumer relationship cleaner and is also useful for CPU related frameworks like OPP to know the frequency at which the CPUs are running. The clock frequency provided by the driver is for each frequency domain. We cannot get the frequency of each CPU core because, not all platforms support per-core DCVS feature. Also the frequency supplied by the driver is the actual frequency that comes out of the EPSS/OSM block after the DCVS operation. This frequency is not same as what the CPUFreq framework has set but it is the one that gets supplied to the CPUs after throttling by LMh. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [ Xiu: Fixed memleak. ] Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: qcom-hw: Fix the frequency returned by cpufreq_driver->get()Manivannan Sadhasivam2022-11-211-13/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpufreq_driver->get() callback is supposed to return the current frequency of the CPU and not the one requested by the CPUFreq core. Fix it by returning the frequency that gets supplied to the CPU after the DCVS operation of EPSS/OSM. Fixes: 2849dd8bc72b ("cpufreq: qcom-hw: Add support for QCOM cpufreq HW driver") Reported-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: qcom-hw: Fix memory leak in qcom_cpufreq_hw_read_lut()Chen Hui2022-11-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If "cpu_dev" fails to get opp table in qcom_cpufreq_hw_read_lut(), the program will return, resulting in "table" resource is not released. Fixes: 51c843cf77bb ("cpufreq: qcom: Update the bandwidth levels on frequency change") Signed-off-by: Chen Hui <judy.chenhui@huawei.com> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: ti: Enable ti-cpufreq for ARCH_K3Dave Gerlach2022-11-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make ti-cpufreq driver depend on ARCH_K3 and set it to `default y` so it is always enabled for platforms that it depends on. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Vibhore Vardhan <vibhore@ti.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: dt-platdev: Blacklist ti,am625 SoCDave Gerlach2022-11-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ti,am625 SoC to the blacklist as the ti-cpufreq driver will handle creating the cpufreq-dt platform device after it completes so it is not created twice. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Vibhore Vardhan <vibhore@ti.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: ti-cpufreq: Add support for AM625Dave Gerlach2022-11-071-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for TI K3 AM625 SoC to read speed and revision values from hardware and pass to OPP layer. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Vibhore Vardhan <vibhore@ti.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: qcom-hw: Move soc_data to struct qcom_cpufreqManivannan Sadhasivam2022-11-021-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | soc_data is a static info of the driver and thus no need to cache it inside the qcom_cpufreq_data struct which is allocated per frequency domain. So, move it inside qcom_cpufreq struct. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: qcom-hw: Use cached dev pointer in probe()Manivannan Sadhasivam2022-11-021-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple instances of dev pointer used in the probe() function. Instead of referencing pdev->dev all the time, let's use a cached dev pointer to simplify the code. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probeManivannan Sadhasivam2022-11-021-49/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qcom_cpufreq_data is allocated based on the number of frequency domains defined in DT which is static and won't change during runtime. There is no real reason to allocate it during the CPU init() callback and deallocate it during exit(). Hence, move the allocation to probe() and use the allocated memory during init(). This also allows us to use devm_platform_get_and_ioremap_resource() helper for acquiring the freq-domain resources from DT. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: qcom-hw: Remove un-necessary cpumask_empty() checkManivannan Sadhasivam2022-11-021-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | CPUFreq core will always set the "policy->cpus" bitmask with the bitfield of the CPU that goes first per domain/policy. So there is no way the "policy->cpus" bitmask will be empty during qcom_cpufreq_hw_cpu_init(). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
| * | cpufreq: Generalize of_perf_domain_get_sharing_cpumask phandle formatHector Martin2022-11-021-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_perf_domain_get_sharing_cpumask currently assumes a 1-argument phandle format, and directly returns the argument. Generalize this to return the full of_phandle_args, so it can be used by drivers which use other phandle styles (e.g. separate nodes). This also requires changing the CPU sharing match to compare the full args structure. Also, make sure to of_node_put(args.np) (the original code was leaking a reference). Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | | cpufreq: intel_pstate: Add Sapphire Rapids support in no-HWP modeGiovanni Gherdovich2022-11-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Users may disable HWP in firmware, in which case intel_pstate wouldn't load unless the CPU model is explicitly supported. See also the following past commits: commit d8de7a44e11f ("cpufreq: intel_pstate: Add Skylake servers support") commit 706c5328851d ("cpufreq: intel_pstate: Add Cometlake support in no-HWP mode") commit fbdc21e9b038 ("cpufreq: intel_pstate: Add Icelake servers support in no-HWP mode") commit 71bb5c82aaae ("cpufreq: intel_pstate: Add Tigerlake support in no-HWP mode") Signed-off-by: Giovanni Gherdovich <ggherdovich@suse.cz> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | cpufreq: amd_freq_sensitivity: Add missing pci_dev_put()Xiongfeng Wang2022-11-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_get_device() will increase the reference count for the returned pci_dev. We need to use pci_dev_put() to decrease the reference count after using pci_get_device(). Let's add it. Fixes: 59a3b3a8db16 ("cpufreq: AMD: Ignore the check for ProcFeedback in ST/CZ") Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | cpufreq: Init completion before kobject_init_and_add()Yongqiang Liu2022-11-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In cpufreq_policy_alloc(), it will call uninitialed completion in cpufreq_sysfs_release() when kobject_init_and_add() fails. And that will cause a crash such as the following page fault in complete: BUG: unable to handle page fault for address: fffffffffffffff8 [..] RIP: 0010:complete+0x98/0x1f0 [..] Call Trace: kobject_put+0x1be/0x4c0 cpufreq_online.cold+0xee/0x1fd cpufreq_add_dev+0x183/0x1e0 subsys_interface_register+0x3f5/0x4e0 cpufreq_register_driver+0x3b7/0x670 acpi_cpufreq_init+0x56c/0x1000 [acpi_cpufreq] do_one_initcall+0x13d/0x780 do_init_module+0x1c3/0x630 load_module+0x6e67/0x73b0 __do_sys_finit_module+0x181/0x240 do_syscall_64+0x35/0x80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Fixes: 4ebe36c94aed ("cpufreq: Fix kobject memleak") Signed-off-by: Yongqiang Liu <liuyongqiang13@huawei.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: 5.2+ <stable@vger.kernel.org> # 5.2+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | Merge back earlier cpufreq material for v6.2.Rafael J. Wysocki2022-11-284-43/+14
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| * | | cpufreq: ACPI: Remove unused variables 'acpi_cpufreq_online' and 'ret'Nathan Chancellor2022-11-161-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang warns: drivers/cpufreq/acpi-cpufreq.c:970:24: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] acpi_cpufreq_online = ret; ^~~ drivers/cpufreq/acpi-cpufreq.c:960:9: note: initialize the variable 'ret' to silence this warning int ret; ^ = 0 1 error generated. Both ret and acpi_cpufreq_online are now unused so they can be safely removed, clearing up the warning. Fixes: 13fdbc8b8da6 ("cpufreq: ACPI: Defer setting boost MSRs") Link: https://github.com/ClangBuiltLinux/linux/issues/1757 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | cpufreq: intel_pstate: Allow EPP 0x80 setting by the firmwareSrinivas Pandruvada2022-11-031-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the "commit 3d13058ed2a6 ("cpufreq: intel_pstate: Use firmware default EPP")" the firmware can set an EPP, which driver will not overwrite. But the driver has a valid range check for: 0x40 > firmware epp < 0x80. Hence firmware can't specify EPP of 0x80. If the firmware didn't specify in the valid range, the driver has a hard coded EPP of 102. But some Chrome hardware vendors don't want this overwrite and wants to boot with chipset default EPP of 0x80 as this improves battery life. In this case they want to have capability to specify EPP of 0x80 via the firmware. This require the valid range to include 0x80 also. But here the valid range can't be simply extended to include 0x80 as this is the chipset default EPP. Even without any firmware specifying EPP, the chipset will always boot with EPP of 0x80. To make sure that firmware specified EPP of 0x80 and not by the chipset default, it will require additional check to make sure HWP was enabled by the firmware before boot. Only way the firmware can update EPP, is to enable HWP and update EPP via MSR_HWP_REQUEST. This driver already checks, if the HWP is enabled by the firmware. Use the same flag and extend valid range to include 0x80. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | cpufreq: ACPI: Defer setting boost MSRsStuart Hayes2022-11-031-28/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When acpi-cpufreq is loaded, boost is enabled on every CPU (by setting an MSR) before the driver is registered with cpufreq. This can be very time consuming, because it is done with a CPU hotplug startup callback, and cpuhp_setup_state() schedules the callback (cpufreq_boost_online()) to run on each CPU one at a time, waiting for each to run before calling the next. If cpufreq_register_driver() fails--if, for example, there are no ACPI P-states present--this is wasted time. Since cpufreq already sets up a CPU hotplug startup callback if and when acpi-cpufreq is registered, set the boost MSRs in acpi_cpufreq_cpu_init(), which is called by the cpufreq cpuhp callback. This allows acpi-cpufreq to exit quickly if it is loaded but not needed. On one system with 192 CPUs, this patch speeds up boot by about 30 seconds. Signed-off-by: Stuart Hayes <stuart.w.hayes@gmail.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | cpufreq: SPEAr: Make read-only array sys_clk_src staticColin Ian King2022-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't populate the read-only array sys_clk_src on the stack but instead make it static and add in a missing const. Also makes the object code a little smaller. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | cpufreq: longhaul: Make array speeds static constColin Ian King2022-11-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't populate the read-only array speeds on the stack but instead make it static. Also makes the object code a little smaller. Replace hard-coded loop array bounds with ARRAY_SIZE. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | cpufreq: ACPI: Use str_enabled_disabled() helperAndy Shevchenko2022-11-031-2/+3
| |/ / | | | | | | | | | | | | | | | | | | Use str_enabled_disabled() helper instead of open coding the same. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | cpufreq: amd-pstate: add amd-pstate driver parameter for mode selectionPerry Yuan2022-11-221-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the amd_pstate driver is built-in users still need a method to be able enable or disable it depending upon their circumstance. Add support for an early parameter to do this. There is some performance degradation on a number of ASICs in the passive mode. This performance issue was originally discovered in shared memory systems but it has been proven that certain workloads on MSR systems also suffer performance issues. Set the amd-pstate driver as disabled by default to temporarily mitigate the performance problem. 1) with `amd_pstate=disable`, pstate driver will be disabled to load at kernel booting. 2) with `amd_pstate=passive`, pstate driver will be enabled and loaded as non-autonomous working mode supported in the low-level power management firmware. 3) If neither parameter is specified, the driver will be disabled by default to avoid triggering performance regressions in certain ASICs Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Tested-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | cpufreq: amd-pstate: change amd-pstate driver to be built-in typePerry Yuan2022-11-222-11/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when the amd-pstate and acpi_cpufreq are both built into kernel as module driver, amd-pstate will not be loaded by default in this case. Change amd-pstate driver as built-in type, it will resolve the loading sequence problem to allow user to make amd-pstate driver as the default cpufreq scaling driver. Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Tested-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Fixes: ec437d71db77 ("cpufreq: amd-pstate: Introduce a new AMD P-State driver to support future processors") Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | cpufreq: amd-pstate: cpufreq: amd-pstate: reset MSR_AMD_PERF_CTL register at ↵Wyes Karny2022-11-221-0/+10
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | init MSR_AMD_PERF_CTL is guaranteed to be 0 on a cold boot. However, on a kexec boot, for instance, it may have a non-zero value (if the cpu was in a non-P0 Pstate). In such cases, the cores with non-P0 Pstates at boot will never be pushed to P0, let alone boost frequencies. Kexec is a common workflow for reboot on Linux and this creates a regression in performance. Fix it by explicitly setting the MSR_AMD_PERF_CTL to 0 during amd_pstate driver init. Cc: All applicable <stable@vger.kernel.org> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Tested-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Wyes Karny <wyes.karny@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | cpufreq: intel_pstate: hybrid: Use known scaling factor for P-coresRafael J. Wysocki2022-10-251-54/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 46573fd6369f ("cpufreq: intel_pstate: hybrid: Rework HWP calibration") attempted to use the information from CPPC (the nominal performance in particular) to obtain the scaling factor allowing the frequency to be computed if the HWP performance level of the given CPU is known or vice versa. However, it turns out that on some platforms this doesn't work, because the CPPC information on them does not align with the contents of the MSR_HWP_CAPABILITIES registers. This basically means that the only way to make intel_pstate work on all of the hybrid platforms to date is to use the observation that on all of them the scaling factor between the HWP performance levels and frequency for P-cores is 78741 (approximately 100000/1.27). For E-cores it is 100000, which is the same as for all of the non-hybrid "core" platforms and does not require any changes. Accordingly, make intel_pstate use 78741 as the scaling factor between HWP performance levels and frequency for P-cores on all hybrid platforms and drop the dependency of the HWP calibration code on CPPC. Fixes: 46573fd6369f ("cpufreq: intel_pstate: hybrid: Rework HWP calibration") Reported-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Tested-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Cc: 5.15+ <stable@vger.kernel.org> # 5.15+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | cpufreq: intel_pstate: Read all MSRs on the target CPURafael J. Wysocki2022-10-251-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the MSR accesses in intel_pstate are carried out on the CPU that is running the code, but the values coming from them are used for the performance scaling of the other CPUs. This is problematic, for example, on hybrid platforms where MSR_TURBO_RATIO_LIMIT for P-cores and E-cores is different, so the values read from it on a P-core are generally not applicable to E-cores and the other way around. For this reason, make the driver access all MSRs on the target CPU on platforms using the "core" pstate_funcs callbacks which is the case for all of the hybrid platforms released to date. For this purpose, pass a CPU argument to the ->get_max(), ->get_max_physical(), ->get_min() and ->get_turbo() pstate_funcs callbacks and from there pass it to rdmsrl_on_cpu() or rdmsrl_safe_on_cpu() to access the MSR on the target CPU. Fixes: 46573fd6369f ("cpufreq: intel_pstate: hybrid: Rework HWP calibration") Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Tested-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Cc: 5.15+ <stable@vger.kernel.org> # 5.15+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | cpufreq: sun50i: Switch to use dev_err_probe() helperYang Yingliang2022-10-181-6/+3
| | | | | | | | | | | | | | | | | | | | In the probe path, convert pr_err() to dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. It's more simple in error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | cpufreq: qcom-nvmem: Switch to use dev_err_probe() helperYang Yingliang2022-10-181-5/+2
| | | | | | | | | | | | | | | | | | | | In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. It's more simple in error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | cpufreq: imx6q: Switch to use dev_err_probe() helperYang Yingliang2022-10-181-3/+1
| | | | | | | | | | | | | | | | | | | | In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. It's more simple in error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | cpufreq: dt: Switch to use dev_err_probe() helperYang Yingliang2022-10-181-4/+2
| | | | | | | | | | | | | | | | | | | | In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. It's more simple in error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | cpufreq: qcom: remove unused parameter in function definitionFabien Parent2022-10-181-4/+4
| | | | | | | | | | | | | | | | | | The speedbin_nvmem parameter is not used for get_krait_bin_format_{a,b}. Let's remove the parameter to make the code cleaner. Signed-off-by: Fabien Parent <fabien.parent@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | cpufreq: qcom: fix writes in read-only memory regionFabien Parent2022-10-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes a kernel oops because of a write in some read-only memory: [ 9.068287] Unable to handle kernel write to read-only memory at virtual address ffff800009240ad8 ..snip.. [ 9.138790] Internal error: Oops: 9600004f [#1] PREEMPT SMP ..snip.. [ 9.269161] Call trace: [ 9.276271] __memcpy+0x5c/0x230 [ 9.278531] snprintf+0x58/0x80 [ 9.282002] qcom_cpufreq_msm8939_name_version+0xb4/0x190 [ 9.284869] qcom_cpufreq_probe+0xc8/0x39c ..snip.. The following line defines a pointer that point to a char buffer stored in read-only memory: char *pvs_name = "speedXX-pvsXX-vXX"; This pointer is meant to hold a template "speedXX-pvsXX-vXX" where the XX values get overridden by the qcom_cpufreq_krait_name_version function. Since the template is actually stored in read-only memory, when the function executes the following call we get an oops: snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d", speed, pvs, pvs_ver); To fix this issue, we instead store the template name onto the stack by using the following syntax: char pvs_name_buffer[] = "speedXX-pvsXX-vXX"; Because the `pvs_name` needs to be able to be assigned to NULL, the template buffer is stored in the pvs_name_buffer and not under the pvs_name variable. Cc: v5.7+ <stable@vger.kernel.org> # v5.7+ Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs") Signed-off-by: Fabien Parent <fabien.parent@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | cpufreq: qcom: fix memory leak in error pathFabien Parent2022-10-181-2/+5
| | | | | | | | | | | | | | | | | | | | | | If for some reason the speedbin length is incorrect, then there is a memory leak in the error path because we never free the speedbin buffer. This commit fixes the error path to always free the speedbin buffer. Cc: v5.7+ <stable@vger.kernel.org> # v5.7+ Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs") Signed-off-by: Fabien Parent <fabien.parent@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | cpufreq: tegra194: Fix module loadingJon Hunter2022-10-181-0/+1
|/ | | | | | | | | | | When the Tegra194 CPUFREQ driver is built as a module it is not automatically loaded as expected on Tegra194 devices. Populate the MODULE_DEVICE_TABLE to fix this. Cc: v5.9+ <stable@vger.kernel.org> # v5.9+ Fixes: df320f89359c ("cpufreq: Add Tegra194 cpufreq driver") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* Merge tag 'char-misc-6.1-rc1' of ↵Linus Torvalds2022-10-081-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc and other driver updates from Greg KH: "Here is the large set of char/misc and other small driver subsystem changes for 6.1-rc1. Loads of different things in here: - IIO driver updates, additions, and changes. Probably the largest part of the diffstat - habanalabs driver update with support for new hardware and features, the second largest part of the diff. - fpga subsystem driver updates and additions - mhi subsystem updates - Coresight driver updates - gnss subsystem updates - extcon driver updates - icc subsystem updates - fsi subsystem updates - nvmem subsystem and driver updates - misc driver updates - speakup driver additions for new features - lots of tiny driver updates and cleanups All of these have been in the linux-next tree for a while with no reported issues" * tag 'char-misc-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (411 commits) w1: Split memcpy() of struct cn_msg flexible array spmi: pmic-arb: increase SPMI transaction timeout delay spmi: pmic-arb: block access for invalid PMIC arbiter v5 SPMI writes spmi: pmic-arb: correct duplicate APID to PPID mapping logic spmi: pmic-arb: add support to dispatch interrupt based on IRQ status spmi: pmic-arb: check apid against limits before calling irq handler spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq spmi: pmic-arb: handle spurious interrupt spmi: pmic-arb: add a print in cleanup_irq drivers: spmi: Directly use ida_alloc()/free() MAINTAINERS: add TI ECAP driver info counter: ti-ecap-capture: capture driver support for ECAP Documentation: ABI: sysfs-bus-counter: add frequency & num_overflows items dt-bindings: counter: add ti,am62-ecap-capture.yaml counter: Introduce the COUNTER_COMP_ARRAY component type counter: Consolidate Counter extension sysfs attribute creation counter: Introduce the Count capture component counter: 104-quad-8: Add Signal polarity component counter: Introduce the Signal polarity component counter: interrupt-cnt: Implement watch_validate callback ...
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