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* crypto: hisilicon - fix spelling mistake "disgest" -> "digest"Colin Ian King2020-01-221-1/+1
| | | | | | | There is a spelling mistake in an error message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - add branch prediction macroZaibo Xu2020-01-161-22/+22
| | | | | | | | This branch prediction macro on the hot path can improve small performance(about 2%) according to the test. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - adjust hpre_crt_para_getZaibo Xu2020-01-161-14/+14
| | | | | | | | Reorder the input parameters of hpre_crt_para_get to make it cleaner. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Fixed some tiny bugs of HPREZaibo Xu2020-01-162-38/+32
| | | | | | | | | 1.Use memzero_explicit to clear key; 2.Fix some little endian writings; 3.Fix some other bugs and stuff of code style; Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Bugfixed tfm leakZaibo Xu2020-01-162-13/+18
| | | | | | | | 1.Fixed the bug of software tfm leakage. 2.Update HW error log message. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Add aead support on SEC2Zaibo Xu2020-01-164-24/+620
| | | | | | | | authenc(hmac(sha1),cbc(aes)), authenc(hmac(sha256),cbc(aes)), and authenc(hmac(sha512),cbc(aes)) support are added for SEC v2. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - redefine skcipher initiationZaibo Xu2020-01-161-35/+61
| | | | | | | | 1.Define base initiation of QP for context which can be reused. 2.Define cipher initiation for other algorithms. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Add branch prediction macroZaibo Xu2020-01-161-14/+14
| | | | | | | | After adding branch prediction for skcipher hot path, a little bit income of performance is gotten. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Add callback error checkZaibo Xu2020-01-162-6/+10
| | | | | | | Add error type parameter for call back checking inside. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Adjust some inner logicZaibo Xu2020-01-161-26/+28
| | | | | | | | 1.Adjust call back function. 2.Adjust parameter checking function. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Update QP resources of SEC V2Zaibo Xu2020-01-163-93/+59
| | | | | | | | | | | | | 1.Put resource including request and resource list into QP context structure to avoid allocate memory repeatedly. 2.Add max context queue number to void kcalloc large memory for QP context. 3.Remove the resource allocation operation. 4.Redefine resource allocation APIs to be shared by other algorithms. 5.Move resource allocation and free inner functions out of operations 'struct sec_req_op', and they are called directly. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Update some names on SEC V2Zaibo Xu2020-01-162-29/+36
| | | | | | | | | | | 1.Adjust dma map function to be reused by AEAD algorithms; 2.Update some names of internal functions and variables to support AEAD algorithms; 3.Rename 'sec_skcipher_exit' as 'sec_skcipher_uninit'; 4.Rename 'sec_get/put_queue_id' as 'sec_alloc/free_queue_id'; Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - fix print/comment of SEC V2Zaibo Xu2020-01-162-6/+6
| | | | | | | Fixed some print, coding style and comments of HiSilicon SEC V2. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Update debugfs usage of SEC V2Zaibo Xu2020-01-163-14/+14
| | | | | | | | | | Applied some advices of Marco Elver on atomic usage of Debugfs, which is carried out by basing on Arnd Bergmann's fixing patch. Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Marco Elver <elver@google.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Herbert Xu2020-01-163-11/+21
|\ | | | | | | Merge crypto tree to pick up hisilicon patch.
| * crypto: hisilicon/sec2 - Use atomics instead of __syncArnd Bergmann2020-01-093-11/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The use of __sync functions for atomic memory access is not supported in the kernel, and can result in a link error depending on configuration: ERROR: "__tsan_atomic32_compare_exchange_strong" [drivers/crypto/hisilicon/sec2/hisi_sec2.ko] undefined! ERROR: "__tsan_atomic64_fetch_add" [drivers/crypto/hisilicon/sec2/hisi_sec2.ko] undefined! Use the kernel's own atomic interfaces instead. This way the debugfs interface actually reads the counter atomically. Fixes: 416d82204df4 ("crypto: hisilicon - add HiSilicon SEC V2 driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | crypto: hisilicon - still no need to check return value of debugfs_create ↵Greg Kroah-Hartman2019-12-201-22/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | functions Just like in 4a97bfc79619 ("crypto: hisilicon - no need to check return value of debugfs_create functions"), there still is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | crypto: hisilicon - select CRYPTO_SKCIPHER, not CRYPTO_BLKCIPHEREric Biggers2019-12-111-1/+1
| | | | | | | | | | | | | | | | | | Another instance of CRYPTO_BLKCIPHER made it in just after it was renamed to CRYPTO_SKCIPHER. Fix it. Fixes: 416d82204df4 ("crypto: hisilicon - add HiSilicon SEC V2 driver") Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | crypto: hisilicon - Remove useless MODULE macrosZhou Wang2019-12-111-4/+0
| | | | | | | | | | | | | | | | | | As we already merge hardware sgl into hisi_qm module, remove useless MODULE macros. Fixes: 48c1cd40fae3 (crypto: hisilicon - merge sgl support to hisi_qm module) Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | crypto: hisilicon - Use the offset fields in sqe to avoid need to split ↵Jonathan Cameron2019-12-113-70/+27
| | | | | | | | | | | | | | | | | | | | | | | | scatterlists We can configure sgl offset fields in ZIP sqe to let ZIP engine read/write sgl data with skipped data. Hence no need to splite the sgl. Fixes: 62c455ca853e (crypto: hisilicon - add HiSilicon ZIP accelerator support) Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | crypto: hisilicon - Fix issue with wrong number of sg elements after dma mapJonathan Cameron2019-12-111-5/+8
|/ | | | | | | | | | | | | | | We fill the hardware scatter gather list assuming it will need the same number of elements at the original scatterlist. If an IOMMU is involved, then it may well need fewer. The return value of dma_map_sg tells us how many. Probably never caused visible problems as the hardware won't get to the elements that are incorrect before it finds enough space. Fixes: dfed0098ab91 (crypto: hisilicon - add hardware SGL support) Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - fix a NULL vs IS_ERR() bug in sec_create_qp_ctx()Dan Carpenter2019-11-271-2/+2
| | | | | | | | | The hisi_acc_create_sgl_pool() function returns error pointers, it never returns NULL pointers. Fixes: 416d82204df4 ("crypto: hisilicon - add HiSilicon SEC V2 driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - add DebugFS for HiSilicon SECZaibo Xu2019-11-223-0/+332
| | | | | | | | | The HiSilicon SEC engine driver uses DebugFS to provide main debug information for user space. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - add SRIOV for HiSilicon SECZaibo Xu2019-11-222-3/+153
| | | | | | | | | | HiSilicon SEC engine supports PCI SRIOV. This patch enable this feature. User can enable VFs and pass through them to VM, same SEC driver can work in VM to provide skcipher algorithms. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - add HiSilicon SEC V2 driverZaibo Xu2019-11-227-0/+1875
| | | | | | | | | | SEC driver provides PCIe hardware device initiation with AES, SM4, and 3DES skcipher algorithms registered to Crypto. It uses Hisilicon QM as interface to CPU. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - no need to check return value of debugfs_create functionsGreg Kroah-Hartman2019-11-172-32/+11
| | | | | | | | | | | | | | When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - add vfs_num module param for zipHao Fang2019-11-171-84/+98
| | | | | | | | | | | | | Currently the VF can be enabled only through sysfs interface after module loaded, but this also needs to be done when the module loaded in some scenarios. This patch adds module param vfs_num, adds hisi_zip_sriov_enable() in probe, and also adjusts the position of probe. Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - replace #ifdef with IS_ENABLED for CONFIG_NUMAZhou Wang2019-11-081-26/+25
| | | | | | | | | | Replace #ifdef CONFIG_NUMA with IS_ENABLED(CONFIG_NUMA) to fix kbuild error. Fixes: 700f7d0d29c7 ("crypto: hisilicon - fix to return...") Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Reported-by: kbuild test robot <lkp@intel.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - fix to return sub-optimal device when best device has no qpsZhou Wang2019-11-013-20/+77
| | | | | | | | | | | | | Currently find_zip_device() finds zip device which has the min NUMA distance with current CPU. This patch modifies find_zip_device to return sub-optimal device when best device has no qps. This patch sorts all devices by NUMA distance, then finds the best zip device which has free qp. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - use sgl API to get sgl dma addr and lenZhou Wang2019-11-012-3/+2
| | | | | | | | | | | Use sgl API to get sgl dma addr and len, this will help to avoid compile error in some platforms. So NEED_SG_DMA_LENGTH can be removed here, which can only be selected by arch code. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Suggested-by: Herbert Xu <herbert@gondor.apana.org.au> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: skcipher - rename the crypto_blkcipher module and kconfig optionEric Biggers2019-11-011-1/+1
| | | | | | | | | | | | Now that the blkcipher algorithm type has been removed in favor of skcipher, rename the crypto_blkcipher kernel module to crypto_skcipher, and rename the config options accordingly: CONFIG_CRYPTO_BLKCIPHER => CONFIG_CRYPTO_SKCIPHER CONFIG_CRYPTO_BLKCIPHER2 => CONFIG_CRYPTO_SKCIPHER2 Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - fix endianness verification problem of QMShukun Tan2019-10-262-44/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes following sparse warning: qm.c:345:33: warning: cast removes address space '<asn:2>' of expression qm.c:359:20: warning: incorrect type in assignment (different base types) qm.c:359:20: expected restricted __le16 [usertype] w0 qm.c:359:20: got int qm.c:362:27: warning: incorrect type in assignment (different base types) qm.c:362:27: expected restricted __le16 [usertype] queue_num qm.c:362:27: got unsigned short [usertype] queue qm.c:363:24: warning: incorrect type in assignment (different base types) qm.c:363:24: expected restricted __le32 [usertype] base_l qm.c:363:24: got unsigned int [usertype] qm.c:364:24: warning: incorrect type in assignment (different base types) qm.c:364:24: expected restricted __le32 [usertype] base_h qm.c:364:24: got unsigned int [usertype] qm.c:451:22: warning: restricted __le32 degrades to integer qm.c:471:24: warning: restricted __le16 degrades to integer ...... qm.c:1617:19: warning: incorrect type in assignment (different base types) qm.c:1617:19: expected restricted __le32 [usertype] dw6 qm.c:1617:19: got int qm.c:1891:24: warning: incorrect type in return expression (different base types) qm.c:1891:24: expected int qm.c:1891:24: got restricted pci_ers_result_t qm.c:1894:40: warning: incorrect type in return expression (different base types) qm.c:1894:40: expected int qm.c:1894:40: got restricted pci_ers_result_t Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - fix param should be static when not external.Shukun Tan2019-10-261-3/+3
| | | | | | | | | | | | | This patch fixes following sparse warning: zip_main.c:87:1: warning: symbol 'hisi_zip_list' was not declared. Should it be static? zip_main.c:88:1: warning: symbol 'hisi_zip_list_lock' was not declared. Should it be static? zip_main.c:948:68: warning: Using plain integer as NULL pointer Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Fix using plain integer as NULL pointerShukun Tan2019-10-261-1/+1
| | | | | | | | | | | This patch fix sparse warning: zip_crypto.c:425:26: warning: Using plain integer as NULL pointer Replaces assignment of 0 to pointer with NULL assignment. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - tiny fix about QM/ZIP error callback printZhou Wang2019-10-262-9/+3
| | | | | | | | | | | Tiny fix to make QM/ZIP error callback print clear and right. If one version hardware does not support error handling, we directly print this. And QM is embedded in ZIP, we can use ZIP print only, so remove unnecessary QM print. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon: Fix misuse of GENMASK macroRikard Falkeborn2019-10-231-2/+2
| | | | | | | | Arguments are supposed to be ordered high then low. Fixes: c8b4b477079d ("crypto: hisilicon - add HiSilicon HPRE accelerator") Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - select NEED_SG_DMA_LENGTH in qm KconfigZhou Wang2019-10-231-0/+1
| | | | | | | | | | To avoid compile error in some platforms, select NEED_SG_DMA_LENGTH in qm Kconfig. Fixes: dfed0098ab91 ("crypto: hisilicon - add hardware SGL support") Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Add debugfs for HPREZaibo Xu2019-10-102-2/+460
| | | | | | | | | HiSilicon HPRE engine driver uses debugfs to provide debug information, the usage can be found in /Documentation/ABI/testing/debugfs-hisi-hpre. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - add SRIOV support for HPREZaibo Xu2019-10-102-7/+133
| | | | | | | | | | | HiSilicon HPRE engine supports PCI SRIOV. This patch enable this feature. User can enable VFs and pass through them to VM, same HPRE driver can work in VM to provide RSA and DH algorithms by crypto akcipher and kpp interfaces. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Hui tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - add HiSilicon HPRE acceleratorZaibo Xu2019-10-106-0/+1702
| | | | | | | | | | | | The HiSilicon HPRE accelerator implements RSA and DH algorithms. It uses Hisilicon QM as interface to CPU. This patch provides PCIe driver to the accelerator and registers its algorithms to crypto akcipher and kpp interfaces. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - misc fix about sglZhou Wang2019-10-101-18/+22
| | | | | | | | | This patch fixes some misc problems in sgl codes, e.g. missing static, sparse error and input parameter check. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - fix large sgl memory allocation problem when disable smmuZhou Wang2019-10-101-15/+68
| | | | | | | | | When disabling SMMU, it may fail to allocate large continuous memory. This patch fixes this by allocating memory as blocks. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - add sgl_sge_nr module param for zipShukun Tan2019-10-103-2/+28
| | | | | | | | Add a module parameter for zip driver to set the number of SGE in one SGL. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - merge sgl support to hisi_qm moduleZhou Wang2019-10-107-84/+58
| | | | | | | | | | | | | | | | As HW SGL can be seen as a data format of QM's sqe, we merge sgl code into qm module and rename it as hisi_qm, which reduces the number of module and make the name less generic. This patch also modify the interface of SGL: - Create/free hisi_acc_sgl_pool inside. - Let user to pass the SGE number in one SGL when creating sgl pool, which is better than a unified module parameter for sgl module before. - Modify zip driver according to sgl interface change. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - allow compile-testing on x86Arnd Bergmann2019-10-052-3/+12
| | | | | | | | | | | | | | | | | To avoid missing arm64 specific warnings that get introduced in this driver, allow compile-testing on all 64-bit architectures. The only actual arm64 specific code in this driver is an open- coded 128 bit MMIO write. On non-arm64 the same can be done using memcpy_toio. What I also noticed is that the mmio store (either one) is not endian-safe, this will only work on little- endian configurations, so I also add a Kconfig dependency on that, regardless of the architecture. Finally, a depenndecy on CONFIG_64BIT is needed because of the writeq(). Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - avoid unused function warningArnd Bergmann2019-09-201-5/+2
| | | | | | | | | | | | | | The only caller of hisi_zip_vf_q_assign() is hidden in an #ifdef, so the function causes a warning when CONFIG_PCI_IOV is disabled: drivers/crypto/hisilicon/zip/zip_main.c:740:12: error: unused function 'hisi_zip_vf_q_assign' [-Werror,-Wunused-function] Replace the #ifdef with an IS_ENABLED() check that leads to the function being dropped based on the configuration. Fixes: 79e09f30eeba ("crypto: hisilicon - add SRIOV support for ZIP") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Fix return value check in hisi_zip_acompress()Yunfeng Ye2019-09-201-2/+2
| | | | | | | | | | | | | | | | | | The return valude of add_comp_head() is int, but @head_size is size_t, which is a unsigned type. size_t head_size; ... if (head_size < 0) // it will never work return -ENOMEM Modify the type of @head_size to int, then change the type to size_t when invoke hisi_zip_create_req() as a parameter. Fixes: 62c455ca853e ("crypto: hisilicon - add HiSilicon ZIP accelerator support") Signed-off-by: Yunfeng Ye <yeyunfeng@huawei.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Matching the dma address for dma_pool_free()Yunfeng Ye2019-09-201-25/+19
| | | | | | | | | | | | When dma_pool_zalloc() fail in sec_alloc_and_fill_hw_sgl(), dma_pool_free() is invoked, but the parameters that sgl_current and sgl_current->next_sgl is not match. Using sec_free_hw_sgl() instead of the original free routine. Fixes: 915e4e8413da ("crypto: hisilicon - SEC security accelerator driver") Signed-off-by: Yunfeng Ye <yeyunfeng@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - Fix double free in sec_free_hw_sgl()Yunfeng Ye2019-09-201-6/+7
| | | | | | | | | | | | | | | | | | | | There are two problems in sec_free_hw_sgl(): First, when sgl_current->next is valid, @hw_sgl will be freed in the first loop, but it free again after the loop. Second, sgl_current and sgl_current->next_sgl is not match when dma_pool_free() is invoked, the third parameter should be the dma address of sgl_current, but sgl_current->next_sgl is the dma address of next chain, so use sgl_current->next_sgl is wrong. Fix this by deleting the last dma_pool_free() in sec_free_hw_sgl(), modifying the condition for while loop, and matching the address for dma_pool_free(). Fixes: 915e4e8413da ("crypto: hisilicon - SEC security accelerator driver") Signed-off-by: Yunfeng Ye <yeyunfeng@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: hisilicon - select CRYPTO_LIB_DES while compiling SEC driverMao Wenan2019-08-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | When CRYPTO_DEV_HISI_SEC=y, below compilation error is found after 'commit 894b68d8be4b ("crypto: hisilicon/des - switch to new verification routines")': drivers/crypto/hisilicon/sec/sec_algs.o: In function `sec_alg_skcipher_setkey_des_cbc': sec_algs.c:(.text+0x11f0): undefined reference to `des_expand_key' drivers/crypto/hisilicon/sec/sec_algs.o: In function `sec_alg_skcipher_setkey_des_ecb': sec_algs.c:(.text+0x1390): undefined reference to `des_expand_key' make: *** [vmlinux] Error 1 This because DES library has been moved to lib/crypto in this commit '04007b0e6cbb ("crypto: des - split off DES library from generic DES cipher driver")'. Fix this by selecting CRYPTO_LIB_DES in CRYPTO_DEV_HISI_SEC. Fixes: 04007b0e6cbb ("crypto: des - split off DES library from generic DES cipher driver") Fixes: 894b68d8be4b ("crypto: hisilicon/des - switch to new verification routines") Signed-off-by: Mao Wenan <maowenan@huawei.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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