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path: root/drivers/crypto/qat/qat_common/qat_hal.c
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* crypto: qat - add support for 401xx devicesGiovanni Cabiddu2022-05-201-0/+1
| | | | | | | | | | QAT_401xx is a derivative of 4xxx. Add support for that device in the qat_4xxx driver by including the DIDs (both PF and VF), extending the probe and the firmware loader. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Srinivas Kerekare <srinivas.kerekare@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add the adf_get_pmisc_base() helper functionMarco Chiappero2021-12-241-30/+11
| | | | | | | | | | | | | | | | Add and use the new helper function adf_get_pmisc_base() where convenient. Also: - remove no longer shared variables - leverage other utilities, such as GET_PFVF_OPS(), as a consequence - consistently use the "pmisc_addr" name for the returned value of this new helper Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - check return code of qat_hal_rd_rel_reg()Jack Xu2021-05-281-1/+5
| | | | | | | | | | | | | | | | Check the return code of the function qat_hal_rd_rel_reg() and return it to the caller. This is to fix the following warning when compiling the driver with clang scan-build: drivers/crypto/qat/qat_common/qat_hal.c:1436:2: warning: 6th function call argument is an uninitialized value Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Zhehui Xiang <zhehui.xiang@intel.com> Signed-off-by: Zhehui Xiang <zhehui.xiang@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - check MMP size before writing to the SRAMJack Xu2021-05-281-4/+4
| | | | | | | | | | | Change "sram_visible" to "mmp_sram_size" and compare it with the MMP size to prevent an overly large MMP file being written to SRAM. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Zhehui Xiang <zhehui.xiang@intel.com> Signed-off-by: Zhehui Xiang <zhehui.xiang@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add gen4 firmware loaderJack Xu2020-11-131-16/+61
| | | | | | | | Add support for the QAT gen4 devices in the firmware loader. Signed-off-by: Jack Xu <jack.xu@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add support for broadcasting modeJack Xu2020-11-131-0/+1
| | | | | | | | | | | Add support for broadcasting mode in firmware loader to enable the next generation of QAT devices. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add support for shared ustoreJack Xu2020-11-131-0/+2
| | | | | | | | | | | Add support for shared ustore mode support. This is required by the next generation of QAT devices to share the same fw image across engines. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - allow to target specific AEsJack Xu2020-11-131-0/+1
| | | | | | | | | | | Introduce new API, qat_uclo_set_cfg_ae_mask(), to allow the load of the firmware image to a subset of Acceleration Engines (AEs). This is required by the next generation of QAT devices to be able to load different firmware images to the device. Signed-off-by: Jack Xu <jack.xu@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add FCU CSRs to chip infoJack Xu2020-11-131-2/+17
| | | | | | | | | | | Add firmware control unit (FCU) CSRs to chip info so the firmware authentication code is common between all devices. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add CSS3K supportJack Xu2020-11-131-0/+2
| | | | | | | | | | | Add support for CSS3K, which uses RSA3K as image signature algorithm, to support the next generation of QAT devices. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add misc control CSR to chip infoJack Xu2020-11-131-4/+7
| | | | | | | | | | | Add misc control CSR to chip info since the CSR offset will be different in the next generation of QAT devices. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add wake up event to chip infoJack Xu2020-11-131-1/+4
| | | | | | | | | | | Add the wake up event to chip info since this value will be different in the next generation of QAT devices. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add clock enable CSR to chip infoJack Xu2020-11-131-4/+6
| | | | | | | | | | | Add global clock enable CSR to the chip info since the CSR offset will be different in the next generation of QAT devices. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add reset CSR and mask to chip infoJack Xu2020-11-131-17/+22
| | | | | | | | | | | | Add reset CSR offset and mask to chip info since they are different in new QAT devices. This also simplifies the reset/clrReset functions by using the reset mask. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add local memory size to chip infoJack Xu2020-11-131-0/+2
| | | | | | | | | | | Add the local memory size to the chip info since the size of this memory will be different in the next generation of QAT devices. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add support for lm2 and lm3Jack Xu2020-11-131-2/+68
| | | | | | | | | | | Add support for local memory lm2 and lm3 which is introduced in the next generation of QAT devices. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add next neighbor to chip_infoJack Xu2020-11-131-1/+10
| | | | | | | | | | | Introduce the next neighbor (NN) capability in chip_info as NN registers are not supported in certain SKUs of QAT. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - introduce chip info structureJack Xu2020-11-131-31/+79
| | | | | | | | | | | | | Introduce the chip info structure which contains device specific information. The initialization path has been split between common and hardware specific in order to facilitate the introduction of the next generation hardware. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - move defines to header filesJack Xu2020-11-131-4/+0
| | | | | | | | | | | | | Move the definition of ICP_QAT_AE_OFFSET, ICP_QAT_CAP_OFFSET, LOCAL_TO_XFER_REG_OFFSET and ICP_QAT_EP_OFFSET from qat_hal.c to icp_qat_hal.h to avoid the definition of generation specific constants in qat_hal.c. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - remove global CSRs helpersJack Xu2020-11-131-10/+10
| | | | | | | | | | | | Include the offset of GLOBAL_CSR directly into the enum hal_global_csr and remove the macros SET_GLB_CSR/GET_GLB_CSR to simplify the global CSR access. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - refactor AE startJack Xu2020-11-131-9/+15
| | | | | | | | | | | | Change the API and the behaviour of the qat_hal_start() function. With this change, the function starts under the hood all acceleration engines (AEs) and there is no longer need to call it for each engine. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - change type for ctx_maskJack Xu2020-11-131-8/+8
| | | | | | | | | | | Change type for ctx_mask from unsigned char to unsigned long to avoid type casting. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - introduce additional parenthesisJack Xu2020-11-131-3/+3
| | | | | | | | | | | Introduce additional parenthesis to resolve a warninga reported by checkpatch. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - remove unnecessary parenthesisJack Xu2020-11-131-3/+3
| | | | | | | | | | Remove unnecessary parenthesis across the firmware loader. Signed-off-by: Jack Xu <jack.xu@intel.com> Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - fix status check in qat_hal_put_rel_rd_xfer()Jack Xu2020-11-131-1/+1
| | | | | | | | | | | | | | | | | The return value of qat_hal_rd_ae_csr() is always a CSR value and never a status and should not be stored in the status variable of qat_hal_put_rel_rd_xfer(). This removes the assignment as qat_hal_rd_ae_csr() is not expected to fail. A more comprehensive handling of the theoretical corner case which could result in a fail will be submitted in a separate patch. Fixes: 8c9478a400b7 ("crypto: qat - reduce stack size with KASAN") Signed-off-by: Jack Xu <jack.xu@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - mask device capabilities with soft strapsGiovanni Cabiddu2020-10-301-12/+15
| | | | | | | | | | | | | | Enable acceleration engines (AEs) and accelerators based on soft straps and fuses. When looping with a number of AEs or accelerators, ignore the ones that are disabled. This patch is based on earlier work done by Conor McLoughlin. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - replace device ids definesGiovanni Cabiddu2020-09-181-3/+4
| | | | | | | | | | Replace device ids defined in the QAT drivers with the ones in include/linux/pci_ids.h. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - replace user types with kernel u typesWojciech Ziemba2020-06-181-20/+20
| | | | | | | | | | Kernel source code should not include stdint.h types. This patch replaces uintXX_t types with respective ones defined in kernel headers. Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - convert to SPDX License IdentifiersGiovanni Cabiddu2020-06-181-46/+2
| | | | | | | Replace License Headers with SPDX License Identifiers. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - reduce stack size with KASANArnd Bergmann2017-12-221-66/+67
| | | | | | | | | | | | | | | Passing the register value by reference here leads a large amount of stack being used when CONFIG_KASAN is enabled: drivers/crypto/qat/qat_common/qat_hal.c: In function 'qat_hal_exec_micro_inst.constprop': drivers/crypto/qat/qat_common/qat_hal.c:963:1: error: the frame size of 1792 bytes is larger than 1536 bytes [-Werror=frame-larger-than=] Changing the register-read function to return the value instead reduces the stack size to around 800 bytes, most of which is for the 'savuwords' array. The function now no longer returns an error code, but nothing ever evaluated that anyway. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - zero esram only for DH85x devicesGiovanni Cabiddu2017-02-021-2/+2
| | | | | | | | | Zero embedded ram in DH85x devices. This is not needed for newer generations as it is done by HW. Cc: <stable@vger.kernel.org> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - update init_esram for C3xxx dev typeTadeusz Struk2016-01-181-0/+3
| | | | | | | | There is no esram on C3xxx devices so we don't need to wait for it to initialize. Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - fix timeout issuesPingchao Yang2016-01-181-5/+6
| | | | | | | | Change the variable times data type and timeout conditon since the value of times should be -1 after loop. Signed-off-by: Yang Pingchao <pingchao.yang@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - remove to call get_sram_bar_id for qat_c3xxxPingchao Yang2016-01-181-3/+6
| | | | | | Reported-by : Struk, Tadeusz <tadeusz.struk@intel.com> Signed-off-by: Yang Pingchao <pingchao.yang@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - fix some timeout testsPingchao Yang2015-12-221-1/+1
| | | | | | | | | Change the timeout condition since the times value would be -1 after running MAX_RETRY_TIMES. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Yang Pingchao <pingchao.yang@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - fix CTX_ENABLES bits shift direction issuePingchao Yang2015-12-221-1/+1
| | | | | | | | | AE CTX bits should be 8-15 in CTX_ENABLES, so the mask value 0xff should be left shifted 0x8. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Yang Pingchao <pingchao.yang@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add support for new devices to FW loaderPingchao Yang2015-12-091-42/+80
| | | | | | | FW loader updates for new qat devices Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - remove unneeded variableTadeusz Struk2015-10-011-3/+2
| | | | | | | | | Remove unneeded variable val_indx. Issue found by a static analyzer. Reported-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - remove unused defineBruce Allan2015-07-281-1/+0
| | | | | | Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - add support for MMP FWPingchao Yang2015-07-171-5/+8
| | | | | | | | | Load Modular Math Processor(MMP) firmware into QAT devices to support public key algorithm acceleration. Signed-off-by: Pingchao Yang <pingchao.yang@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - fix checkpatch BIT_MACRO issuesAllan, Bruce W2015-04-011-2/+2
| | | | | | | CHECK:BIT_MACRO: Prefer using the BIT macro Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - make error and info log messages more descriptiveAllan, Bruce W2015-03-231-1/+1
| | | | | | | | | | | Convert pr_info() and pr_err() log messages to dev_info() and dev_err(), respectively, where able. This adds the module name and PCI B:D:F to indicate which QAT device generated the log message. The "QAT:" is removed from these log messages as that is now unnecessary. A few of these log messages have additional spelling/contextual fixes. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - Move BAR definitions to device specific moduleTadeusz Struk2014-11-061-1/+2
| | | | | | | Move PCI BARs definitions to device specific module where it belongs. Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - Use hweight for bit countingTadeusz Struk2014-08-011-13/+2
| | | | | | | | Use predefined hweight32 function instead of writing a new one. Signed-off-by: Pingchao Yang <pingchao.yang@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - Updated print outputsTadeusz Struk2014-08-011-2/+1
| | | | | | | | Updated pr_err output to make it more consistent. Signed-off-by: Pingchao Yang <pingchao.yang@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - change ae_num to ae_idTadeusz Struk2014-08-011-13/+13
| | | | | | | | | | Change the logic how acceleration engines are indexed to make it easier to read. Aslo some return code values updates to better reflect what failed. Signed-off-by: Pingchao Yang <pingchao.yang@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - remove an unneeded castDan Carpenter2014-07-101-1/+1
| | | | | | | The cast to (unsigned int *) doesn't hurt anything but it is pointless. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - Fixed new checkpatch warningsTadeusz Struk2014-06-261-2/+5
| | | | | | | | After updates to checkpatch new warnings pops up this patch fixes them. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Acked-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - Intel(R) QAT accelengine part of fw loaderTadeusz Struk2014-06-201-0/+1402
This patch adds acceleration engine handler part the firmware loader. Acked-by: Bo Cui <bo.cui@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Karen Xiang <karen.xiang@intel.com> Signed-off-by: Pingchaox Yang <pingchaox.yang@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-18 12:04:13 +0000