| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | cxl/pci: Map registers based on capabilities | Ira Weiny | 2021-06-05 | 1 | -21/+90 | |
| * | cxl/pci: Reserve all device regions at once | Ira Weiny | 2021-06-05 | 1 | -7/+11 | |
| * | cxl/pci: Introduce cxl_decode_register_block() | Ira Weiny | 2021-06-05 | 1 | -8/+18 | |
| * | cxl/mem: Get rid of @cxlm.base | Ben Widawsky | 2021-05-26 | 1 | -13/+11 | |
| * | cxl/mem: Move register locator logic into reg setup | Ben Widawsky | 2021-05-26 | 1 | -67/+68 | |
| * | cxl/mem: Split creation from mapping in probe | Ben Widawsky | 2021-05-26 | 1 | -24/+40 | |
| * | cxl/mem: Use dev instead of pdev->dev | Ben Widawsky | 2021-05-26 | 1 | -1/+1 | |
| * | cxl/pci.c: Add a 'label_storage_size' attribute to the memdev | Vishal Verma | 2021-05-26 | 1 | -0/+12 | |
| * | cxl: Rename mem to pci | Ben Widawsky | 2021-05-26 | 1 | -0/+1524 | |
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index : Linux | |
| Linux kernel mainline tree | Linus Torvalds |
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