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	Commit message (Collapse)	Author	Age	Files	Lines
*	dmaengine: mediatek: hsdma_probe: fixed a memory leak when devm_request_irq ↵	Satendra Singh Thakur	2019-11-14	1	-1/+3
\| \| \| \| \| \| \| \| \| \| \| \| \|	fails When devm_request_irq fails, currently, the function dma_async_device_unregister gets called. This doesn't free the resources allocated by of_dma_controller_register. Therefore, we have called of_dma_controller_free for this purpose. Signed-off-by: Satendra Singh Thakur <sst2005@gmail.com> Link: https://lore.kernel.org/r/20191109113523.6067-1-sst2005@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
*	cross-tree: phase out dma_zalloc_coherent()	Luis Chamberlain	2019-01-08	1	-2/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	We already need to zero out memory for dma_alloc_coherent(), as such using dma_zalloc_coherent() is superflous. Phase it out. This change was generated with the following Coccinelle SmPL patch: @ replace_dma_zalloc_coherent @ expression dev, size, data, handle, flags; @@ -dma_zalloc_coherent(dev, size, handle, flags) +dma_alloc_coherent(dev, size, handle, flags) Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Luis Chamberlain <mcgrof@kernel.org> [hch: re-ran the script on the latest tree] Signed-off-by: Christoph Hellwig <hch@lst.de>
*	dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and ↵	Sean Wang	2018-03-27	1	-0/+1056
	MT7623 SoC MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has a single ring is dedicated to memory-to-memory transfer through ring based descriptor management. Even though there is only one physical ring available inside HSDMA, the driver can be easily extended to the support of multiple virtual channels processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Fengguang Wu <fengguang.wu@intel.com> Cc: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>