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* dmaengine: stm32-dma: Add PM Runtime supportPierre-Yves MORDRET2019-01-071-7/+51
| | | | | | | Use pm_runtime engine for clock management purpose. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: stm32-dma: check FIFO error interrupt enablePierre-Yves MORDRET2019-01-071-5/+8
| | | | | | | | | For avoiding false FIFO detection, check FIFO Error interrupt is enabled prior raising any errors. This will prevent having spurious FIFO error where it shouldn't. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: stm32-dma: check whether length is aligned on FIFO thresholdPierre-Yves MORDRET2018-10-021-14/+6
| | | | | | | | | | | | | When a period length is not multiple of FIFO some data may be stuck within FIFO. Burst/FIFO Threshold/Period or buffer length check has to be hardened In any case DMA will grant any request from client but will degraded any parameters whether awkward. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: stm32: replace "%p" with "%pK"Benjamin Gaignard2018-07-091-2/+2
| | | | | | | | The format specifier "%p" can leak kernel addresses. Use "%pK" instead. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: stm32-dma: properly mask irq bitsPierre Yves MORDRET2018-04-041-1/+6
| | | | | | | | | | | | | | | | | | A single register of the controller holds the information for four dma channels. The functions stm32_dma_irq_status() don't mask the relevant bits after the shift, thus adjacent channel's status is also reported in the returned value. Fixed by masking the value before returning it. Similarly, the function stm32_dma_irq_clear() don't mask the input value before shifting it, thus an incorrect input value could disable the interrupts of adjacent channels. Fixed by masking the input value before using it. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: fix max items per transferPierre Yves MORDRET2018-04-041-8/+11
| | | | | | | | | | Having 0 in item counter register is valid and stands for a "No or Ended transfer". Therefore valid transfer starts from @+0 to @+0xFFFE leading to unaligned scatter gather at boundary. Thus it's safer to round down this value on its FIFO size (16 Bytes). Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: fix DMA IRQ status handlingPierre Yves MORDRET2018-04-041-4/+25
| | | | | | | | | Update the way Transfer Complete and Half Transfer Complete status are acknowledge. Even if HTI is not enabled its status is shown when reading registers, driver has to clear it gently and not raise an error. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: Improve memory burst managementPierre Yves MORDRET2018-04-041-29/+175
| | | | | | | | | | | | | This patch improves memory burst capability using best burst size according to transferred buffer size from/to memory. >From now on, memory burst is not necessarily same as with peripheral burst one and fifo threshold is directly managed by this driver in order to fit with computed memory burst. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: fix typo and reported checkpatch warningsPierre Yves MORDRET2018-04-041-5/+6
| | | | | | | Fix typo in a comment and solved reported checkpatch warnings. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: fix incomplete configuration in cyclic modePierre Yves MORDRET2018-04-041-2/+6
| | | | | | | | | | When in cyclic mode, the configuration is updated after having started the DMA hardware (STM32_DMA_SCR_EN) leading to incomplete configuration of SMxAR registers. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: threshold manages with bitfield featurePierre Yves MORDRET2018-04-041-3/+16
| | | | | | | >From now on, DMA bitfield is to manage DMA FIFO Threshold. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: fix up error dev_err messageColin Ian King2017-03-061-1/+1
| | | | | | | Trivial fix to spelling mistake and make channel plural. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge tag 'dmaengine-4.11-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2017-02-211-29/+59
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: "This time we fairly boring and bit small update. - Support for Intel iDMA 32-bit hardware - deprecate broken support for channel switching in async_tx - bunch of updates on stm32-dma - Cyclic support for zx dma and making in generic zx dma driver - Small updates to bunch of other drivers" * tag 'dmaengine-4.11-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (29 commits) async_tx: deprecate broken support for channel switching dmaengine: rcar-dmac: Widen DMA mask to 40 bits dmaengine: sun6i: allow build on ARM64 platforms (sun50i) dmaengine: Provide a wrapper for memcpy operations dmaengine: zx: fix build warning dmaengine: dw: we do support Merrifield SoC in PCI mode dmaengine: dw: add support of iDMA 32-bit hardware dmaengine: dw: introduce register mappings for iDMA 32-bit dmaengine: dw: introduce block2bytes() and bytes2block() dmaengine: dw: extract dwc_chan_pause() for future use dmaengine: dw: replace convert_burst() with one liner dmaengine: dw: register IRQ and DMA pool with instance ID dmaengine: dw: Fix data corruption in large device to memory transfers dmaengine: ste_dma40: indicate granularity on channels dmaengine: ste_dma40: indicate directions on channels dmaengine: stm32-dma: Add error messages if xlate fails dmaengine: dw: pci: remove LPE Audio DMA ID dmaengine: stm32-dma: Add max_burst support dmaengine: stm32-dma: Add synchronization support dmaengine: stm32-dma: Fix residue computation issue in cyclic mode ...
| * dmaengine: stm32-dma: Add error messages if xlate failsM'boumba Cedric Madianga2017-01-101-9/+15
| | | | | | | | | | | | | | | | | | This patch adds some error messages when a slave device fails to request a channel. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Reviewed-by: Ludovic BARRE <ludovic.barre@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: stm32-dma: Add max_burst supportM'boumba Cedric Madianga2017-01-031-0/+2
| | | | | | | | | | | | | | This patch sets the max_burst value supported by the STM32 DMA Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: stm32-dma: Add synchronization supportM'boumba Cedric Madianga2017-01-031-0/+8
| | | | | | | | | | | | | | | | Implement the new device_synchronize() callback to allow proper synchronization when stopping a channel. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: stm32-dma: Fix residue computation issue in cyclic modeM'boumba Cedric Madianga2017-01-031-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | This patch resolves the residue computation issue detected in cyclic mode. Now, in cyclic mode, we increment next_sg variable as soon as a period is transferred instead of after pushing a new sg request. Then, we take into account that after transferring a complete buffer, the next_sg variable is equal to 0. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Reviewed-by: Ludovic BARRE <ludovic.barre@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: stm32-dma: Rework starting transfer managementM'boumba Cedric Madianga2017-01-031-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the way to manage transfer starting. Now, starting DMA is only allowed when the channel is not busy. Then, stm32_dma_start_transfer is declared as void. At least, after each transfer completion, we start the next transfer if a new descriptor as been queued in the issued list during an ongoing transfer. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Reviewed-by: Ludovic BARRE <ludovic.barre@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: stm32-dma: Fix null pointer dereference in stm32_dma_tx_statusM'boumba Cedric Madianga2017-01-021-7/+3
| | | | | | | | | | | | | | | | | | | | | | chan->desc is always set to NULL when a DMA transfer is complete. As a DMA transfer could be complete during the call of stm32_dma_tx_status, we need to be sure that chan->desc is not NULL before using this variable to avoid a null pointer deference issue. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Reviewed-by: Ludovic BARRE <ludovic.barre@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: stm32-dma: Set correct args number for DMA request from DTM'boumba Cedric Madianga2017-01-021-5/+2
|/ | | | | | | | | This patch sets the right number of arguments to be used for DMA clients which request channels from DT. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Reviewed-by: Ludovic BARRE <ludovic.barre@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: remove unused ‘src_addr’Vinod Koul2016-12-121-2/+0
| | | | | | | | | | | | | | In stm32_dma_set_xfer_param(), variable ‘src_addr’ is initialized but never used, which leads to warning with W=1 drivers/dma/stm32-dma.c: In function ‘stm32_dma_set_xfer_param’: drivers/dma/stm32-dma.c:577:13: warning: variable ‘src_addr’ set but not used [-Wunused-but-set-variable] dma_addr_t src_addr, dst_addr; So remove it. Reviewed-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: remove unused ‘dst_addr’Vinod Koul2016-12-121-2/+1
| | | | | | | | | | | | | | In stm32_dma_set_xfer_param(), variable ‘dst_addr’ is initialized but never used, which leads to warning with W=1 drivers/dma/stm32-dma.c: In function ‘stm32_dma_set_xfer_param’: drivers/dma/stm32-dma.c:577:23: warning: variable ‘dst_addr’ set but not used [-Wunused-but-set-variable] dma_addr_t src_addr, dst_addr; So remove it. Reviewed-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: remove unused ‘sfcr’Vinod Koul2016-12-121-2/+1
| | | | | | | | | | | | | | In stm32_dma_chan_irq(), variable ‘sfcr’ is initialized but never used, which leads to warning with W=1 drivers/dma/stm32-dma.c: In function ‘stm32_dma_chan_irq’: drivers/dma/stm32-dma.c:530:19: warning: variable ‘sfcr’ set but not used [-Wunused-but-set-variable] u32 status, scr, sfcr; So remove it. Reviewed-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: make stm32_dma_set_config staticVinod Koul2016-09-261-1/+1
| | | | | | | | | | Sparse complains: drivers/dma/stm32-dma.c:957:6: warning: symbol 'stm32_dma_set_config' was not declared. Should it be static? SO make stm32_dma_set_config static. Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: stm32-dma: Fix unchecked deference of chan->descM'boumba Cedric Madianga2015-12-101-2/+2
| | | | | | | | | | | | | | | | 'commit d8b468394fb7 ("dmaengine: Add STM32 DMA driver")' leads to the following Smatch complaint: drivers/dma/stm32-dma.c:562 stm32_dma_issue_pending() error: we previously assumed 'chan->desc' could be null (see line 560) So, this patch fixes the unchecked dereference of chan->desc by returning operation not permitted error when stm32_dma_start_transfer() does not succeed to allocate a virtual channel descriptor. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: Add STM32 DMA driverM'boumba Cedric Madianga2015-11-161-0/+1141
This patch adds support for the STM32 DMA controller. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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