summaryrefslogtreecommitdiffstats
path: root/drivers/fpga
Commit message (Expand)AuthorAgeFilesLines
* fpga: altera-hps2fpga: fix multiple init of l3_remap_lockIan Abbott2017-08-101-3/+1
* fpga: altera-hps2fpga: add NULL check on of_match_device() return valueGustavo A. R. Silva2017-08-101-0/+5
* ARM: socfpga: explicitly request exclusive reset controlPhilipp Zabel2017-08-101-1/+2
* fpga: Convert to using %pOF instead of full_nameRob Herring2017-08-101-2/+2
* fpga manager: Add Altera CvP driverAnatolij Gustschin2017-07-173-0/+508
* fpga-manager: altera-ps-spi: use bitrev8x4Joshua Clayton2017-07-171-4/+15
* fpga manager: Add altera-ps-spi driver for Altera FPGAsJoshua Clayton2017-07-173-0/+305
* Make FPGA a menuconfig to ease disabling it allVincent Legoll2017-07-171-5/+1
* fpga fr br: update supported version numbersMatthew Gerlach2017-04-261-11/+19
* fpga: region: release FPGA region reference in error pathTobias Klauser2017-04-261-1/+3
* fpga altera-hps2fpga: disable/unprepare clock on error in alt_fpga_bridge_pro...Tobias Klauser2017-04-261-6/+9
* fpga: Add support for Xilinx LogiCORE PR DecouplerMoritz Fischer2017-04-083-0/+172
* fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.Matthew Gerlach2017-04-083-0/+76
* fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.Matthew Gerlach2017-04-083-0/+226
* fpga: add config complete timeoutAlan Tull2017-04-081-0/+3
* fpga manager: Add Xilinx slave serial SPI driverAnatolij Gustschin2017-04-083-0/+206
* fpga: altera_freeze_bridge: Constify opsMoritz Fischer2017-04-081-1/+1
* fpga: bridge: Replace open-coded list_for_each + list_entryMoritz Fischer2017-03-171-11/+4
* fpga: Add support for Lattice iCE40 FPGAsJoel Holdsworth2017-03-173-0/+214
* FPGA: Add TS-7300 FPGA managerFlorian Fainelli2017-03-173-0/+164
* fpga: region: Add fpga-region property 'encrypted-fpga-config'Moritz Fischer2017-03-171-2/+6
* fpga: zynq: Add support for encrypted bitstreamsMoritz Fischer2017-03-171-3/+25
* fpga: fix sparse warnings in fpga-mgr and fpga-bridgeDinh Nguyen2017-03-172-2/+2
* fpga zynq: Use the scatterlist interfaceJason Gunthorpe2017-02-101-39/+135
* fpga: Add scatterlist based programmingJason Gunthorpe2017-02-101-30/+206
* fpga zynq: Check the bitstream for validityJason Gunthorpe2017-02-101-0/+21
* fpga zynq: Check for errors after completing DMAJason Gunthorpe2017-02-101-22/+32
* fpga: Clarify how write_init works streaming modesJason Gunthorpe2016-11-292-2/+5
* fpga zynq: Fix incorrect ISR state on bootupJason Gunthorpe2016-11-291-7/+10
* fpga zynq: Remove priv->devJason Gunthorpe2016-11-291-11/+8
* fpga zynq: Add missing \n to messagesJason Gunthorpe2016-11-291-11/+11
* fpga: Add COMPILE_TEST to all driversJason Gunthorpe2016-11-291-2/+3
* ARM: socfpga: checking the wrong variableDan Carpenter2016-11-171-1/+1
* fpga-manager: Add Socfpga Arria10 supportAlan Tull2016-11-103-0/+563
* fpga: add altera freeze bridge supportAlan Tull2016-11-103-0/+283
* ARM: socfpga: fpga bridge driver supportAlan Tull2016-11-104-0/+410
* fpga: fpga-region: device tree control for FPGAAlan Tull2016-11-103-0/+613
* fpga: add fpga bridge frameworkAlan Tull2016-11-103-0/+405
* fpga-mgr: add fpga image information structAlan Tull2016-11-103-15/+19
* fpga: add method to get fpga manager from deviceAlan Tull2016-11-101-22/+54
* fpga manager: Add hardware dependency to Zynq driverJean Delvare2016-09-081-0/+1
* drivers/fpga/Kconfig: fix build failureSudip Mukherjee2016-08-041-0/+1
* fpga manager: Fix firmware resource leak on errorTobias Klauser2015-11-241-3/+1
* fpga manager: remove labelAlan Tull2015-11-241-6/+3
* fpga: socfpga: Fix check of return value of devm_request_irqMoritz Fischer2015-10-291-1/+1
* fpga: zynq-fpga: Fix issue with drvdata being overwritten.Moritz Fischer2015-10-231-3/+4
* fpga manager: remove unnecessary null pointer checksAlan Tull2015-10-231-8/+4
* fpga manager: ensure lifetime with of_fpga_mgr_getAlan Tull2015-10-231-15/+17
* fpga: zynq-fpga: Change fw format to handle bin instead of bit.Moritz Fischer2015-10-231-22/+2
* fpga: zynq-fpga: Fix unbalanced clock handlingMoritz Fischer2015-10-231-2/+2
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 11:24:29 +0000