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* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
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* Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/s...Linus Torvalds2019-05-163-0/+169
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| * fpga manager: Adding FPGA Manager support for Xilinx zynqmpNava kishore Manne2019-04-153-0/+169
* | mm/gup: change GUP fast to use flags rather than a write 'bool'Ira Weiny2019-05-141-1/+1
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* Merge 5.0-rc6 into char-misc-nextGreg Kroah-Hartman2019-02-111-4/+1
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| * fpga: stratix10-soc: fix wrong of_node_put() in init functionNicolas Saenz Julienne2019-01-311-4/+1
* | fpga: altera_freeze_bridge: remove restriction to socfpgaAlan Tull2019-01-311-1/+1
* | fpga: mgr: altera-ps-spi: make array dummy static, shrinks object sizeColin Ian King2019-01-311-1/+1
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* Remove 'type' argument from access_ok() functionLinus Torvalds2019-01-032-3/+2
* fpga: of-fpga-region: Use platform_set_drvdataMoritz Fischer2018-11-261-1/+1
* fpga: dfl-fme-region: Use platform_get_drvdata()Moritz Fischer2018-11-261-1/+1
* fpga: add intel stratix10 soc fpga manager driverAlan Tull2018-11-263-0/+542
* fpga: mgr: altera-ps-spi: enable usage on non-dt platformsAnatolij Gustschin2018-11-261-5/+35
* fpga: altera-cvp: fix probing for multiple FPGAs on the busAnatolij Gustschin2018-11-261-10/+24
* zynq-fpga: Only route PR via PCAP when requiredMike Looijmans2018-11-111-0/+4
* fpga: altera-cvp: Fix registration for CvP incapable devicesAndreas Puhm2018-11-111-0/+9
* fpga: dfl: fme: remove set but not used variable 'priv'YueHaibing2018-11-111-2/+0
* fpga: altera-cvp: fix 'bad IO access' on x86_64Anatolij Gustschin2018-11-111-2/+4
* fpga: add devm_fpga_region_createAlan Tull2018-10-164-20/+63
* fpga: bridge: add devm_fpga_bridge_createAlan Tull2018-10-166-38/+73
* fpga: mgr: add devm_fpga_mgr_createAlan Tull2018-10-1612-80/+87
* Merge 4.19-rc7 into char-misc-nextGreg Kroah-Hartman2018-10-083-3/+6
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| * fpga: bridge: fix obvious function documentation errorAlan Tull2018-09-301-1/+1
| * fpga: do not access region struct after fpga_region_unregisterAlan Tull2018-09-302-2/+5
* | Merge b4.19-rc4 into char-misc-nextGreg Kroah-Hartman2018-09-161-1/+1
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| * fpga: dfl: fme: fix return value check in in pr_mgmt_init()Wei Yongjun2018-09-121-1/+1
* | drivers: fpga: fix two trivial spelling mistakesColin Ian King2018-09-122-2/+2
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* Merge 4.18-rc5 into char-misc-nextGreg Kroah-Hartman2018-07-161-2/+4
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| * fpga: altera-cvp: Fix an error handling path in 'altera_cvp_probe()'Christophe Jaillet2018-07-071-2/+4
* | fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls supportWu Hao2018-07-154-3/+554
* | fpga: dfl: afu: add afu sub feature supportXiao Guangrong2018-07-154-7/+451
* | fpga: dfl: afu: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls supportWu Hao2018-07-151-0/+11
* | fpga: dfl: afu: add header sub feature supportWu Hao2018-07-151-1/+78
* | fpga: dfl: afu: add port ops supportWu Hao2018-07-151-1/+121
* | fpga: dfl: add FPGA Accelerated Function Unit driver basic frameworkWu Hao2018-07-153-0/+173
* | fpga: dfl: fme-region: add support for compat_idWu Hao2018-07-151-0/+1
* | fpga: dfl: add fpga region platform driver for FMEWu Hao2018-07-153-0/+95
* | fpga: dfl: add fpga bridge platform driver for FMEWu Hao2018-07-153-0/+121
* | fpga: dfl: fme-mgr: add compat_id supportWu Hao2018-07-151-0/+15
* | fpga: dfl: add fpga manager platform driver for FMEWu Hao2018-07-153-0/+341
* | fpga: dfl: fme: add partial reconfiguration sub feature supportKang Luwei2018-07-155-2/+644
* | fpga: dfl: fme: add DFL_FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls supportWu Hao2018-07-151-0/+12
* | fpga: dfl: fme: add header sub feature supportKang Luwei2018-07-151-0/+68
* | fpga: dfl: add FPGA Management Engine driver basic frameworkKang Luwei2018-07-153-0/+171
* | fpga: dfl-pci: add enumeration for feature devicesWu Hao2018-07-151-2/+142
* | fpga: add FPGA DFL PCIe device driverZhang Yi2018-07-153-0/+121
* | fpga: dfl: add dfl_fpga_check_port_id function.Wu Hao2018-07-152-0/+23
* | fpga: dfl: add dfl_fpga_port_ops support.Wu Hao2018-07-152-0/+100
* | fpga: dfl: add feature device infrastructureXiao Guangrong2018-07-152-1/+152
* | fpga: dfl: add dfl_fpga_cdev_find_portWu Hao2018-07-152-0/+53
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