summaryrefslogtreecommitdiffstats
path: root/drivers/fpga
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'arm-drivers-5.13' of ↵Linus Torvalds2021-04-261-4/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "Updates for SoC specific drivers include a few subsystems that have their own maintainers but send them through the soc tree: TEE/OP-TEE: - Add tracepoints around calls to secure world Memory controller drivers: - Minor fixes for Renesas, Exynos, Mediatek and Tegra platforms - Add debug statistics to Tegra20 memory controller - Update Tegra bindings and convert to dtschema ARM SCMI Firmware: - Support for modular SCMI protocols and vendor specific extensions - New SCMI IIO driver - Per-cpu DVFS The other driver changes are all from the platform maintainers directly and reflect the drivers that don't fit into any other subsystem as well as treewide changes for a particular platform. SoCFPGA: - Various cleanups contributed by Krzysztof Kozlowski Mediatek: - add MT8183 support to mutex driver - MMSYS: use per SoC array to describe the possible routing - add MMSYS support for MT8183 and MT8167 - add support for PMIC wrapper with integrated arbiter - add support for MT8192/MT6873 Tegra: - Bug fixes to PMC and clock drivers NXP/i.MX: - Update SCU power domain driver to keep console domain power on. - Add missing ADC1 power domain to SCU power domain driver. - Update comments for single global power domain in SCU power domain driver. - Add i.MX51/i.MX53 unique id support to i.MX SoC driver. NXP/FSL SoC driver updates for v5.13 - Add ACPI support for RCPM driver - Use generic io{read,write} for QE drivers after performance optimized for PowerPC - Fix QBMAN probe to cleanup HW states correctly for kexec - Various cleanup and style fix for QBMAN/QE/GUTS drivers OMAP: - Preparation to use devicetree for genpd - ti-sysc needs iorange check improved when the interconnect target module has no control registers listed - ti-sysc needs to probe l4_wkup and l4_cfg interconnects first to avoid issues with missing resources and unnecessary deferred probe - ti-sysc debug option can now detect more devices - ti-sysc now warns if an old incomplete devicetree data is found as we now rely on it being complete for am3 and 4 - soc init code needs to check for prcm and prm nodes for omap4/5 and dra7 - omap-prm driver needs to enable autoidle retention support for omap4 - omap5 clocks are missing gpmc and ocmc clock registers - pci-dra7xx now needs to use builtin_platform_driver instead of using builtin_platform_driver_probe for deferred probe to work Raspberry Pi: - Fix-up all RPi firmware drivers so as for unbind to happen in an orderly fashion - Support for RPi's PoE hat PWM bus Qualcomm - Improved detection for SCM calling conventions - Support for OEM specific wifi firmware path - Added drivers for SC7280/SM8350: RPMH, LLCC< AOSS QMP" * tag 'arm-drivers-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits) soc: aspeed: fix a ternary sign expansion bug memory: mtk-smi: Add device-link between smi-larb and smi-common memory: samsung: exynos5422-dmc: handle clk_set_parent() failure memory: renesas-rpc-if: fix possible NULL pointer dereference of resource clk: socfpga: fix iomem pointer cast on 64-bit soc: aspeed: Adapt to new LPC device tree layout pinctrl: aspeed-g5: Adapt to new LPC device tree layout ipmi: kcs: aspeed: Adapt to new LPC DTS layout ARM: dts: Remove LPC BMC and Host partitions dt-bindings: aspeed-lpc: Remove LPC partitioning soc: fsl: enable acpi support in RCPM driver soc: qcom: mdt_loader: Detect truncated read of segments soc: qcom: mdt_loader: Validate that p_filesz < p_memsz soc: qcom: pdr: Fix error return code in pdr_register_listener firmware: qcom_scm: Fix kernel-doc function names to match firmware: qcom_scm: Suppress sysfs bind attributes firmware: qcom_scm: Workaround lack of "is available" call on SC7180 firmware: qcom_scm: Reduce locking section for __get_convention() firmware: qcom_scm: Make __qcom_scm_is_call_available() return bool Revert "soc: fsl: qe: introduce qe_io{read,write}* wrappers" ...
| * fpga: altera: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCsKrzysztof Kozlowski2021-03-231-3/+3
| | | | | | | | | | | | | | | | | | ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the 32-bit ARM drivers to rely on new symbol. Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| * arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGAKrzysztof Kozlowski2021-03-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Agilex, N5X and Stratix 10 share all quite similar arm64 hard cores and SoC-part. Up to a point that N5X uses the same DTSI as Agilex. From the Linux kernel point of view these are flavors of the same architecture so there is no need for three top-level arm64 architectures. Simplify this by merging all three architectures into ARCH_INTEL_SOCFPGA and dropping the other ARCH* arm64 Kconfig entries. The side effect is that the INTEL_STRATIX10_SERVICE will now be available for both 32-bit and 64-bit Intel SoCFPGA, even though it is used only for 64-bit. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | fpga: dfl: pci: add DID for D5005 PAC cardsRuss Weight2021-04-051-7/+11
| | | | | | | | | | | | | | | | | | This patch adds the approved PCI Express Device IDs for the PF and VF for the card for D5005 PAC cards. Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* | fpga: dfl: afu: harden port enable logicRuss Weight2021-03-243-16/+31
| | | | | | | | | | | | | | | | | | | | | | | | Port enable is not complete until ACK = 0. Change __afu_port_enable() to guarantee that the enable process is complete by polling for ACK == 0. Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* | fpga: Add support for Xilinx DFX AXI Shutdown managerNava kishore Manne2021-03-062-6/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Xilinx Dynamic Function eXchange(DFX) AXI shutdown manager IP. It can be used to safely handling the AXI traffic on a Reconfigurable Partition when it is undergoing dynamic reconfiguration and there by preventing system deadlock that may occur if AXI transactions are interrupted during reconfiguration. PR-Decoupler and AXI shutdown manager are completely different IPs. But both the IP registers are compatible and also both belong to the same sub-system (fpga-bridge).So using same driver for both IP's. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* | fpga: xilinx-pr-decoupler: Simplify code by using dev_err_probe()Michal Simek2021-03-061-5/+3
| | | | | | | | | | | | | | | | | | Use already prepared dev_err_probe() introduced by commit a787e5400a1c ("driver core: add device probe log helper"). It simplifies EPROBE_DEFER handling. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* | fpga: fpga-mgr: xilinx-spi: fix error messages on -EPROBE_DEFERLuca Ceresoli2021-03-061-15/+9
|/ | | | | | | | | | | | | | | | The current code produces an error message on devm_gpiod_get() errors even when the error is -EPROBE_DEFER, which should be silent. This has been observed producing a significant amount of messages like: xlnx-slave-spi spi1.1: Failed to get PROGRAM_B gpio: -517 Fix and simplify code by using the dev_err_probe() helper function. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during write_init") Fixes: 061c97d13f1a ("fpga manager: Add Xilinx slave serial SPI driver") Signed-off-by: Moritz Fischer <mdf@kernel.org>
* Merge tag 'fpga-cleanup-for-5.12' of ↵Greg Kroah-Hartman2021-01-122-6/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next Moritz writes: First set of FPGA Manager changes for 5.12-rc1 This is the first set of changes for the FPGA Manager 5.12-rc1 mergewindow. DFL: - Minor cleanup, constifying a static attribute group Core: - Minor cleanup, using DEFINE_SPINLOCK over open coding it All patches have been reviewed on the mailing list, and have been in the last linux-next releases (as part of my for-next branch) without issues. Signed-off-by: Moritz Fischer <mdf@kernel.org> * tag 'fpga-cleanup-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: fpga: dfl: fme: Constify static attribute_group structs fpga: Use DEFINE_SPINLOCK() for spinlock
| * fpga: dfl: fme: Constify static attribute_group structsRikard Falkeborn2021-01-101-3/+3
| | | | | | | | | | | | | | | | | | | | The only usage of these is to put their addresses in arrays of pointers to const attribute_groups. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
| * fpga: Use DEFINE_SPINLOCK() for spinlockZheng Yongjun2021-01-101-3/+1
| | | | | | | | | | | | | | | | | | spinlock can be initialized automatically with DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init(). Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* | fpga: dfl: add support for N3000 Nios private featureXu Yilun2021-01-073-0/+601
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Nios handshake private feature on Intel PAC (Programmable Acceleration Card) N3000. The Nios is the embedded processor on the FPGA card. This private feature provides a handshake interface to FPGA Nios firmware, which receives retimer configuration command from host and executes via an internal SPI master (spi-altera). When Nios finishes the configuration, host takes over the ownership of the SPI master to control an Intel MAX10 BMC (Board Management Controller) Chip on the SPI bus. For Nios firmware handshake part, this driver requests the retimer configuration for Nios firmware on probe, and adds some sysfs nodes for user to query the onboard retimer's working mode and Nios firmware version. For SPI part, this driver adds a spi-altera platform device as well as the MAX10 BMC spi slave info. A spi-altera driver will be matched to handle the following SPI work. [mdf@kernel.org: Fixed up ABI doc kernel release] Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20210107043714.991646-8-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: dfl: move dfl bus related APIs to include/linux/dfl.hXu Yilun2021-01-072-72/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the dfl drivers could be made as independent modules and put in different folders according to their functionalities. In order for scattered dfl device drivers to include dfl bus APIs, move the dfl bus APIs to a new header file in the public folder. [mdf@kernel.org: Fixed up header guards to match filename] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20210107043714.991646-7-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: dfl: move dfl_device_id to mod_devicetable.hXu Yilun2021-01-071-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support MODULE_DEVICE_TABLE() for dfl device driver, this patch moves struct dfl_device_id to mod_devicetable.h Some brief description for DFL (Device Feature List) is added to make the DFL known to the whole kernel. Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20210107043714.991646-5-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: dfl: fix the definitions of type & feature_id for dfl devicesXu Yilun2021-01-072-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value of the field dfl_device.type comes from the 12 bits register field DFH_ID according to DFL spec. So this patch changes the definition of the type field to u16. Also it is not necessary to illustrate the valid bits of the type field in comments. Instead we should explicitly define the possible values in the enumeration type for it, because they are shared by hardware spec. We should not let the compiler decide these values. Similar changes are also applied to dfl_device.feature_id. This patch also fixed the MODALIAS format according to the changes above. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20210107043714.991646-4-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: dfl-pci: locate DFLs by PCIe vendor specific capabilityMatthew Gerlach2021-01-071-1/+86
| | | | | | | | | | | | | | | | | | | | A PCIe vendor specific extended capability is introduced by Intel to specify the start of a number of DFLs. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20210107043714.991646-3-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: dfl: refactor cci_enumerate_feature_devs()Matthew Gerlach2021-01-071-37/+47
|/ | | | | | | | | | | | In preparation of looking for dfls based on a vendor specific pci capability, move the code for the default method of finding the first dfl at offset 0 of Bar 0 to its own function. Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20210107043714.991646-2-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge 5.10-rc7 into char-misc-nextGreg Kroah-Hartman2020-12-071-0/+1
|\ | | | | | | | | | | | | We want the fixes in here, and this resolves a merge issue with drivers/misc/habanalabs/common/memory.c. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * fpga: Specify HAS_IOMEM dependency for FPGA_DFLDavid Gow2020-12-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because dfl.c uses the 'devm_ioremap', 'devm_iounmap', 'devm_ioremap_resource', and 'devm_platform_ioremap_resource' functions, it should depend on HAS_IOMEM. This fixes make allyesconfig under UML (ARCH=um), which doesn't provide HAS_IOMEM. [mdf@kernel.org: Removed "drivers: " in commit message] Fixes: 89eb35e810a8 ("fpga: dfl: map feature mmio resources in their own feature drivers") Signed-off-by: David Gow <davidgow@google.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201122001549.107023-2-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: altera-pr-ip: Simplify registrationMoritz Fischer2020-12-012-13/+1
| | | | | | | | | | | | | | | | | | Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-11-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: zynqmp: Simplify registrationMoritz Fischer2020-12-011-20/+1
| | | | | | | | | | | | | | | | | | Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-10-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: xilinx-spi: Simplify registrationMoritz Fischer2020-12-011-13/+1
| | | | | | | | | | | | | | | | | | Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: ts73xx: Simplify registrationMoritz Fischer2020-12-011-13/+1
| | | | | | | | | | | | | | | | | | Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-8-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: socfpga: Simplify registrationMoritz Fischer2020-12-011-13/+1
| | | | | | | | | | | | | | | | | | Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-7-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: machxo2-spi: Simplify registrationMoritz Fischer2020-12-011-13/+1
| | | | | | | | | | | | | | | | | | Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-6-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: ice40-spi: Simplify registrationMoritz Fischer2020-12-011-13/+1
| | | | | | | | | | | | | | | | | | Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-5-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: dfl-fme-mgr: Simplify registrationMoritz Fischer2020-12-011-12/+1
| | | | | | | | | | | | | | | | | | Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-4-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: altera-ps-spi: Simplify registrationMoritz Fischer2020-12-011-13/+1
| | | | | | | | | | | | | | | | | | Simplify registration by using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-3-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | fpga: fpga-mgr: Add devm_fpga_mgr_register() APIMoritz Fischer2020-12-011-12/+69
|/ | | | | | | | | | | | | | Add a devm_fpga_mgr_register() API that can be used to register a FPGA Manager that was created using devm_fpga_mgr_create(). Introduce a struct fpga_mgr_devres that makes the devres allocation a little bit more readable and gets reused for devm_fpga_mgr_create() devm_fpga_mgr_register(). Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20201115195127.284487-2-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* fpga: dfl: create a dfl bus type to support DFL devicesXu Yilun2020-09-092-8/+343
| | | | | | | | | | | | | | | | | | | | A new bus type "dfl" is introduced for private features which are not initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these private features could be handled by separate driver modules. DFL feature drivers (dfl-fme, dfl-port) will create DFL devices on enumeration. DFL drivers could be registered on this bus to match these DFL devices. They are matched by dfl type & feature_id. [mdf@kernel.org: Add missing Documentation part to MAINTAINERS file] Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga: fpga-region: Cleanup an outdated commentMoritz Fischer2020-09-041-1/+1
| | | | | | | Clean up an outdated comment claiming FPGA regions implement devicetree support for reprogramming FPGAs. Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga: dfl: map feature mmio resources in their own feature driversXu Yilun2020-08-303-77/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes preparation for modularization of DFL sub feature drivers. DFL based FPGA devices may contain some IP blocks which are already supported by kernel, most of them are supported by platform device drivers. We could create platform devices for these IP blocks and get them supported by these drivers. An important issue is that platform device drivers usually requests mmio resources on probe. But now DFL mmio is mapped in DFL bus driver (e.g. dfl-pci) as a whole region. Then platform device drivers for sub features can't request their own mmio resources again. This is what the patch trying to resolve. This patch changes the DFL enumeration. DFL bus driver will unmap mmio resources after first step enumeration and pass enumeration info to DFL framework. Then DFL framework will map the mmio resources again, do 2nd step enumeration, and also unmap the mmio resources. In this way, sub feature drivers could then request their own mmio resources as needed. An exception is that mmio resource of FIU headers are still mapped in DFL bus driver. The FIU headers have some fundamental functions (sriov set, port enable/disable) needed for DFL bus devices and other sub features. They should not be unmapped as long as DFL bus device is alive. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga manager: xilinx-spi: provide better diagnostics on programming failureLuca Ceresoli2020-08-301-1/+15
| | | | | | | | | | When the DONE pin does not go high after programming to confirm programming success, the INIT_B pin provides some info on the reason. Use it if available to provide a more explanatory error message. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga manager: xilinx-spi: add error checking after gpiod_get_value()Luca Ceresoli2020-08-301-8/+27
| | | | | | | | | | | | Current code calls gpiod_get_value() without error checking. Should the GPIO controller fail, execution would continue without any error message. Fix by checking for negative error values. Reported-by: Tom Rix <trix@redhat.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga manager: xilinx-spi: fix write_complete timeout handlingLuca Ceresoli2020-08-301-8/+15
| | | | | | | | | | | | | | | | | | | | If this routine sleeps because it was scheduled out, it might miss DONE going asserted and consider it a timeout. This would potentially make the code return an error even when programming succeeded. Rewrite the loop to always check DONE after checking if timeout expired so this cannot happen anymore. While there, also add error checking for gpiod_get_value(). Also avoid checking the DONE GPIO in two places, which would make the error-checking code duplicated and more annoying. The new loop it written to still guarantee that we apply 8 extra CCLK cycles after DONE has gone asserted, which is required by the hardware. Reported-by: Tom Rix <trix@redhat.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga manager: xilinx-spi: remove final dot from dev_err() stringsLuca Ceresoli2020-08-301-2/+2
| | | | | | | | | Most dev_err messages in this file have no final dot. Remove the only two exceptions to make them consistent. Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga manager: xilinx-spi: remove stray commentLuca Ceresoli2020-08-191-1/+0
| | | | | | | | Remove comment committed by mistake. Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during write_init") Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga: dfl: change data type of feature id to u16Xu Yilun2020-08-193-20/+21
| | | | | | | | | | | | The feature id is stored in a 12 bit field in DFH. So a u16 variable is enough for feature id. This patch changes all feature id related places to fit u16. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* fpga: stratix10-soc: make FPGA task un-interruptibleRichard Gong2020-08-191-20/+3
| | | | | | | | | | | | | When CTRL+C occurs during the process of FPGA reconfiguration, the FPGA reconfiguration process stops and the user can't perform a new FPGA reconfiguration properly. Set FPGA task to be not interruptible so that the user can properly perform FPGA reconfiguration after CTRL+C event. Signed-off-by: Richard Gong <richard.gong@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* Merge 5.8-rc7 into char-misc-nextGreg Kroah-Hartman2020-07-272-2/+4
|\ | | | | | | | | | | | | | | This should resolve the merge/build issues reported when trying to create linux-next. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * fpga: dfl: fix bug in port reset handshakeMatthew Gerlach2020-07-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | When putting the port in reset, driver must wait for the soft reset acknowledgment bit instead of the soft reset bit. Fixes: 47c1b19c160f (fpga: dfl: afu: add port ops support) Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Wu Hao <hao.wu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
| * fpga: dfl: pci: reduce the scope of variable 'ret'Xu Yilun2020-07-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is to fix lkp cppcheck warnings: drivers/fpga/dfl-pci.c:230:6: warning: The scope of the variable 'ret' can be reduced. [variableScope] int ret = 0; ^ drivers/fpga/dfl-pci.c:230:10: warning: Variable 'ret' is assigned a value that is never used. [unreadVariable] int ret = 0; ^ Fixes: 3c2760b78f90 ("fpga: dfl: pci: fix return value of cci_pci_sriov_configure") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Wu Hao <hao.wu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
* | Merge tag 'fpga-for-5.9' of ↵Greg Kroah-Hartman2020-07-2311-43/+574
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next Moritz writes: FPGA Manager changes for 5.9-rc1 Here is the (slightly larger than usual) patch set for the 5.9-rc1 merge window. DFL: - Xu's changes add support for AFU interrupt handling and puts them to use for error handling. - Xu's other change also adds another device-id for the Intel FPGA PAC N3000. - John's change converts from using get_user_pages() to pin_user_pages(). - Gustavo's patch cleans up some of the allocation by using struct_size(). Xilinx: - Luca's changes clean up the xilinx-spi and xilinx-slave-serial drivers and updates the comments and dt-bindings to reflect the fact it also supports 7 series devices. Core: - Tom cleaned up the fpga-bridge / fpga-mgr core by removing some dead-stores. All patches have been reviewed on the mailing list, and have been in the last few linux-next releases (as part of my for-next branch) without issues. Signed-off-by: Moritz Fischer <mdf@kernel.org> * tag 'fpga-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: fpga: dfl: pci: add device id for Intel FPGA PAC N3000 Documentation: fpga: dfl: add descriptions for interrupt related interfaces. fpga: dfl: afu: add AFU interrupt support fpga: dfl: fme: add interrupt support for global error reporting fpga: dfl: afu: add interrupt support for port error reporting fpga: dfl: introduce interrupt trigger setting API fpga: dfl: pci: add irq info for feature devices enumeration fpga: dfl: parse interrupt info for feature devices on enumeration fpga manager: xilinx-spi: check INIT_B pin during write_init dt-bindings: fpga: xilinx-slave-serial: add optional INIT_B GPIO fpga: Fix dead store in fpga-bridge.c fpga: Fix dead store fpga-mgr.c fpga: dfl: Use struct_size() in kzalloc() fpga manager: xilinx-spi: remove unneeded, mistyped variables fpga manager: xilinx-spi: valid for the 7 Series too dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too fpga: dfl: afu: convert get_user_pages() --> pin_user_pages()
| * fpga: dfl: pci: add device id for Intel FPGA PAC N3000Xu Yilun2020-07-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add PCIe Device ID for Intel FPGA PAC N3000. Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Wu Hao <hao.wu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
| * fpga: dfl: afu: add AFU interrupt supportXu Yilun2020-07-061-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AFU (Accelerated Function Unit) is dynamic region of the DFL based FPGA, and always defined by users. Some DFL based FPGA cards allow users to implement their own interrupts in AFU. In order to support this, hardware implements a new UINT (AFU Interrupt) private feature with related capability register which describes the number of supported AFU interrupts as well as the local index of the interrupts for software enumeration, and from software side, driver follows the common DFL interrupt notification and handling mechanism, and it implements two ioctls below for user to query number of irqs supported and set/unset interrupt triggers. Ioctls: * DFL_FPGA_PORT_UINT_GET_IRQ_NUM get the number of irqs, which is used to determine how many interrupts UINT feature supports. * DFL_FPGA_PORT_UINT_SET_IRQ set/unset eventfds as AFU interrupt triggers. Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
| * fpga: dfl: fme: add interrupt support for global error reportingXu Yilun2020-07-062-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Error reporting interrupt is very useful to notify users that some errors are detected by the hardware. Once users are notified, they could query hardware logged error states, no need to continuously poll on these states. This patch adds interrupt support for fme global error reporting sub feature. It follows the common DFL interrupt notification and handling mechanism. And it implements two ioctls below for user to query number of irqs supported, and set/unset interrupt triggers. Ioctls: * DFL_FPGA_FME_ERR_GET_IRQ_NUM get the number of irqs, which is used to determine whether/how many interrupts fme error reporting feature supports. * DFL_FPGA_FME_ERR_SET_IRQ set/unset given eventfds as fme error reporting interrupt triggers. Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
| * fpga: dfl: afu: add interrupt support for port error reportingXu Yilun2020-07-062-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Error reporting interrupt is very useful to notify users that some errors are detected by the hardware. Once users are notified, they could query hardware logged error states, no need to continuously poll on these states. This patch adds interrupt support for port error reporting sub feature. It follows the common DFL interrupt notification and handling mechanism, implements two ioctl commands below for user to query number of irqs supported, and set/unset interrupt triggers. Ioctls: * DFL_FPGA_PORT_ERR_GET_IRQ_NUM get the number of irqs, which is used to determine whether/how many interrupts error reporting feature supports. * DFL_FPGA_PORT_ERR_SET_IRQ set/unset given eventfds as error interrupt triggers. Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
| * fpga: dfl: introduce interrupt trigger setting APIXu Yilun2020-06-282-0/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FPGA user applications may be interested in interrupts generated by DFL features. For example, users can implement their own FPGA logics with interrupts enabled in AFU (Accelerated Function Unit, dynamic region of DFL based FPGA). So user applications need to be notified to handle these interrupts. In order to allow userspace applications to monitor interrupts, driver requires userspace to provide eventfds as interrupt notification channels. Applications then poll/select on the eventfds to get notified. This patch introduces a generic helper functions to do eventfds binding with given interrupts. Sub feature drivers are expected to use XXX_GET_IRQ_NUM to query irq info, and XXX_SET_IRQ to set eventfds for interrupts. This patch also introduces helper functions for these 2 ioctls. Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
| * fpga: dfl: pci: add irq info for feature devices enumerationXu Yilun2020-06-281-9/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some DFL FPGA PCIe cards (e.g. Intel FPGA Programmable Acceleration Card) support MSI-X based interrupts. This patch allows PCIe driver to prepare and pass interrupt resources to DFL via enumeration API. These interrupt resources could then be assigned to actual features which use them. Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
| * fpga: dfl: parse interrupt info for feature devices on enumerationXu Yilun2020-06-282-0/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DFL based FPGA devices could support interrupts for different purposes, but current DFL framework only supports feature device enumeration with given MMIO resources information via common DFL headers. This patch introduces one new API dfl_fpga_enum_info_add_irq for low level bus drivers (e.g. PCIe device driver) to pass its interrupt resources information to DFL framework for enumeration, and also adds interrupt enumeration code in framework to parse and assign interrupt resources for enumerated feature devices and their own sub features. With this patch, DFL framework enumerates interrupt resources for core features, including PORT Error Reporting, FME (FPGA Management Engine) Error Reporting and also AFU User Interrupts. Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 21:59:38 +0000