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* drm/amdgpu/kiq: add no_scheduler flag to KIQAlex Deucher2020-04-131-0/+1
| | | | | | | | We don't want a GPU scheduler for this ring. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: rework sched_list generationNirmoy Das2020-04-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: call ras_debugfs_create_all in debugfs_initTao Zhou2020-03-101-1/+0
| | | | | | | | | | | | and remove each ras IP's own debugfs creation this is required to fix ras when the driver does not use the drm load and unload callbacks due to ordering issues with the drm device node. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: set compute queue priority at mqd_initNirmoy Das2020-03-091-0/+8
| | | | | | | | | | | | | | | | | | We were changing compute ring priority while rings were being used before every job submission which is not recommended. This patch sets compute queue priority at mqd initialization for gfx8, gfx9 and gfx10. Policy: make queue 0 of each pipe as high priority compute queue High/normal priority compute sched lists are generated from set of high/normal priority compute queues. At context creation, entity of compute queue get a sched list from high or normal priority depending on ctx->priority Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: use amdgpu_ring_test_helper when possibleNirmoy Das2020-02-261-1/+1
| | | | | | | | amdgpu_ring_test_helper already handles ring->sched.ready correctly Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: provide a generic function interface for reading/writing ↵chen gong2020-01-221-2/+94
| | | | | | | | | | | | | | register by KIQ Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c, and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and flexible. Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: cover the powerplay implementation details V3Evan Quan2020-01-141-6/+0
| | | | | | | | | | | | | This can save users much troubles. As they do not actually need to care whether swSMU or traditional powerplay routine should be used. V2: apply the fixes to vi.c and cik.c also V3: squash in oops fix Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: drop useless BACO arg in amdgpu_ras_reset_gpuGuchun Chen2019-12-181-1/+1
| | | | | | | | | | BACO reset mode strategy is determined by latter func when calling amdgpu_ras_reset_gpu. So not to confuse audience, drop it. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gfx10: fix out-of-bound mqd_backup array accessXiaojie Yuan2019-11-221-2/+0
| | | | | | | Fixes: 0900a9efdb7909 ("drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings (v2)") Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings (v2)Xiaojie Yuan2019-11-221-1/+1
| | | | | | | | | | | 1. no need to allocate an extra member for 'mqd_backup' array 2. backup/restore mqd to/from the correct 'mqd_backup' array slot v2: warning fix (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: remove unused parameter in amdgpu_gfx_kiq_free_ringNirmoy Das2019-10-251-2/+1
| | | | | | Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: remove set but not used variable 'pipe'yu kuai2019-10-031-3/+1
| | | | | | | | | | | | | | | Fixes gcc '-Wunused-but-set-variable' warning: rivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_graphics_queue_acquire’: drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:234:16: warning: variable ‘pipe’ set but not used [-Wunused-but-set-variable] It is never used, so can be removed. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: yu kuai <yukuai3@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add comments in ras interrupt callbackTao Zhou2019-10-031-1/+6
| | | | | | | | add comments to clarify why checking GFX IP BLOCK for each ras interrupt callback Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: remove ih_info parameter of gfx_ras_late_initTao Zhou2019-10-031-9/+7
| | | | | | | | gfx_ras_late_init can get the info by itself Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add common gfx_ras_fini functionTao Zhou2019-10-031-0/+15
| | | | | | | | gfx_ras_fini can be shared among all generations of gfx Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: move gfx ecc functions to generic gfx fileTao Zhou2019-10-031-0/+33
| | | | | | | | gfx ras ecc common functions could be reused among all gfx generations Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gfx: switch to amdgpu_gfx_ras_late_init helper functionHawking Zhang2019-09-131-0/+49
| | | | | | | | | | amdgpu_gfx_ras_late_init is used to init gfx specfic ras debugfs/sysfs node and gfx specific interrupt handler. It can be shared among gfx generations Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable async gfx ring for navi14Xiaojie Yuan2019-07-181-3/+3
| | | | | | | | Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'drm-next' into drm-next-5.3Alex Deucher2019-06-251-1/+1
|\ | | | | | | | | | | Backmerge drm-next and fix up conflicts due to drmP.h removal. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd: drop use of drmP.h in amdgpu/amdgpu*Sam Ravnborg2019-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop use of drmP.h in all files named amdgpu* in drm/amd/amdgpu/ Fix fallout. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-10-sam@ravnborg.org
* | drm/amd: add gfxoff support on navi10Kenneth Feng2019-06-211-1/+3
| | | | | | | | | | | | | | | | add the gfxoff interface to navi10,it's disabled by default. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: create mqd for gfx queues on navi10Hawking Zhang2019-06-201-1/+34
| | | | | | | | | | | | | | | | | | | | mqd is the memory queue descriptor for gfx and compute. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/gfx10: add special unmap_queues packet for preemptionJack Xiao2019-06-201-1/+2
| | | | | | | | | | | | | | | | | | CP introduced a special unmap_queues packet for gfx preemtion. Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: Move common code to amdgpu_gfx.cHawking Zhang2019-06-201-0/+47
| | | | | | | | | | | | | | | | | | | | | | move common code to amdgpu_gfx_enable_kcq,so this function can be shared with gfx8 and gfx9 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: Add common gfx func Disable kcq via kiqRex Zhu2019-06-201-0/+19
| | | | | | | | | | | | | | | | | | so can be shared with gfx8 and gfx9 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: rename amdgpu_gfx_compute_mqd_sw_initHawking Zhang2019-06-201-4/+4
| | | | | | | | | | | | | | | | | | | | The function now will create mqd bos for both gfx queue and compute queue Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add helper function for gfx queue/bitmap transitionHawking Zhang2019-06-201-6/+36
| | | | | | | | | | | | | | | | | | | | Similar to what we do for compute already. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: acquire available gfx queuesHawking Zhang2019-06-201-0/+24
|/ | | | | | | | | | | | | currently, amdgpu will owns the first gfx queue of each pipe they are: me:0 pipe:0 queue:0 me:0 pipe:1 queue:0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add limit of pp_feature for smu (v3)Likun Gao2019-03-191-1/+1
| | | | | | | | | | | | | | | | Move pp_feature from the struct of amd_powerplay to amdgpu_device. Add pp_feature limit for overdrive interface. v2: put pp_feature into struct amdgpu_pm. v3: merge feature_mask with pp_feature. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Use asic specific doorbell index instead of macro definitionOak Zeng2018-11-281-1/+1
| | | | | | | | | | ASIC specific doorbell layout is used instead of enum definition Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: separate amdgpu_rlc into a single fileLikun Gao2018-11-091-0/+1
| | | | | | | | | | Separate the function and struct of RLC from the file of GFX. Abstract the function of amdgpu_gfx_rlc_fini. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Fix null point errorRex Zhu2018-10-241-1/+1
| | | | | | | | | | need to check adev->powerplay.pp_funcs first, becasue from AI, the smu ip can be disabled by user, and the pp_handle is null in this case. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Delay 100ms to enable gfx off featureRex Zhu2018-08-271-2/+2
| | | | | | | | Original 500ms delay seems a bit large. Change to 100 ms suggested by Christian. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: move gfx definitions into amdgpu_gfx headerHuang Rui2018-08-271-1/+33
| | | | | | | | Demangle amdgpu.h Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Put enable gfx off feature to a delay threadRex Zhu2018-08-271-2/+6
| | | | | | | | | | delay to enable gfx off feature to avoid gfx on/off frequently suggested by Alex and Evan. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add amdgpu_gfx_off_ctrl functionRex Zhu2018-08-271-0/+36
| | | | | | | | | | | | | | | | v2: 1. drop the special handling for the hw IP suggested by hawking and Christian. 2. refine the variable name suggested by Flora. This funciton as the entry of gfx off feature. we arbitrat gfx off feature enable/disable in this function. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: use queue 0 for kiq ringHuang Rui2018-01-291-2/+6
| | | | | | | | | | It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on queue 0. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: rename amdgpu_wb_* functionsAlex Deucher2017-12-181-2/+2
| | | | | | | add device for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: busywait KIQ register accessing (v4)pding2017-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | Register accessing is performed when IRQ is disabled. Never sleep in this function. Known issue: dead sleep in many use cases of index/data registers. v2: - wrap polling fence functions. - don't trigger IRQ for polling in case of wrongly fence signal. v3: - handle wrap round gracefully. - add comments for polling function v4: - don't return negative timeout confused with error code Signed-off-by: pding <Pixel.Ding@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add option for force enable multipipe policy for computeAndres Rodriguez2017-09-281-0/+6
| | | | | | | | Useful for testing the effects of multipipe compute without recompiling. Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: use multipipe compute policy on non PL11 asicsAndres Rodriguez2017-09-281-2/+12
| | | | | | | | | | | A performance regression for OpenCL tests on Polaris11 had this feature disabled for all asics. Instead, disable it selectively on the affected asics. Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/sriov:alloc KIQ MQD in VRAM(v2)Monk Liu2017-09-261-1/+6
| | | | | | | | | | | | | | this way after KIQ MQD released in drv unloading, CPC can still let KIQ access this MQD thus RLCV SAVE_VF will not fail v2: always use VRAM domain for KIQ MQD no matter BM or SRIOV Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gfx: keep all compute queues on the same pipeAlex Deucher2017-07-141-1/+2
| | | | | | | | | Spreading them causes performance regressions using compute queues on Polaris 11. Cc: Jim Qu <jim.qu@amd.com> Acked-by: Jim Qu <Jim.Qu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/amdgpu: Rename KIQ ring to avoid spacesTom St Denis2017-06-151-1/+1
| | | | | | | | Swap space for underscore in ring name. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gfx: consolidate mqd buffer setup codeAlex Deucher2017-06-071-0/+66
| | | | | | | It was duplicated across multiple generations. Reviewed-by: Alex Xie <AlexBin.Xie@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.cAlex Deucher2017-06-071-0/+103
| | | | | | | Lots more common stuff. Reviewed-by: Alex Xie <AlexBin.Xie@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: move gfx_v*_0_compute_queue_acquire to common codeAlex Deucher2017-06-071-0/+37
| | | | | | | Same function was duplicated in all gfx IP files. Reviewed-by: Alex Xie <AlexBin.Xie@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: simplify allocation of scratch regsNils Wallménius2017-01-271-14/+7
| | | | | | | | | | | The scratch regs are sequential so there's no need to keep them in an array, we can just return the index of the first free register + the base register. Also change the array of bools for keeping track of the free regs to a bitfield. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: change function declarations and add missing header dependenciesBaoyou Xie2016-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | We get a few warnings when building kernel with W=1: drivers/gpu/drm/amd/amdgpu/atombios_crtc.c:38:6: warning: no previous prototype for 'amdgpu_atombios_crtc_overscan_setup' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/dce_v8_0.c:661:6: warning: no previous prototype for 'dce_v8_0_disable_dce' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:40:5: warning: no previous prototype for 'amdgpu_gfx_scratch_get' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:62:6: warning: no previous prototype for 'amdgpu_gfx_scratch_free' [-Wmissing-prototypes] .... In fact, these functions are declared in drivers/gpu/drm/amd/amdgpu/atombios_crtc.h drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h drivers/gpu/drm/amd/amdgpu/dce_v8_0.h drivers/gpu/drm/amd/amdgpu/dce_v10_0.h drivers/gpu/drm/amd/amdgpu/dce_v11_0.h drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h. So this patch adds missing header dependencies. By the way, this patch changes declaration of amdgpu_gfx_parse_disable_cu() to subject to its implement, and clean three function declarations in pp_acpi.h up. Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add disable_cu parameterNicolai Hähnle2016-07-071-0/+44
| | | | | | | | | This parameter will allow disabling individual CUs on module load, e.g. amdgpu.disable_cu=2.0.3,2.0.4 to disable CUs 3 and 4 of SE2. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-28 11:45:57 +0000