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path: root/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
Commit message (Expand)AuthorAgeFilesLines
* drm/amdgpu: Reorder uvd ring init before uvd resumeChris Wilson2018-11-281-4/+4
* drm/amdgpu: Modify the argument of emit_ib interfaceRex Zhu2018-11-051-1/+2
* drm/amdgpu: further ring test cleanupsChristian König2018-11-051-12/+4
* drm/amdgpu: Retire amdgpu_ring.ready flag v4Andrey Grodzovsky2018-11-051-6/+3
* drm/amdgpu: move more defines into amdgpu_irq.hChristian König2018-09-261-1/+1
* drm/amdgpu/uvd: UVD entity initialization relys on ring initializationEmily Deng2018-08-131-0/+4
* drm/amd: Use newly added interrupt source defs for VI v3.Andrey Grodzovsky2018-07-131-1/+2
* drm/amdgpu: fix insert nop for UVD5 ringLeo Liu2018-05-181-2/+13
* drm/amdgpu/vg20:Restruct uvd to support multiple uvdsJames Zhu2018-05-181-12/+13
* drm/amdgpu: remove now superflous *_hdp operationChristian König2018-02-191-30/+0
* drm/amdgpu: rename vm_id to vmidChristian König2017-12-271-1/+1
* drm/amd/amdgpu: fix UVD mc offsetsPiotr Redlewski2017-12-061-1/+1
* drm/amdgpu: change redundant init logs to debug levelpding2017-12-041-1/+1
* drm/amdgpu: various cleanups for uvd/vce.Rex Zhu2017-04-041-15/+3
* drm/amdgpu: switch ih handling to two levels (v3)Alex Deucher2017-03-291-1/+1
* drm/amdgpu: change wptr to 64 bits (v2)Ken Wang2017-03-291-4/+5
* drm/amdgpu: read hw register to check pg status.Rex Zhu2017-02-131-3/+2
* drm/amdgpu: refine uvd5.0/6.0 code.Rex Zhu2017-02-081-14/+10
* drm/amdgpu: add get clockgating_state method for uvd v5&v6Huang Rui2017-01-271-2/+31
* drm/amdgpu: remove static integer for uvd pp stateYintian Tao2017-01-061-5/+0
* drm/amdgpu: fix bug mclk can't change on PolarisRex Zhu2016-12-061-2/+4
* drm/amdgpu: refine uvd 5.0 clock gate feature.Rex Zhu2016-11-111-23/+83
* drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0Rex Zhu2016-11-111-15/+0
* drm/amdgpu: enable uvd bypass mode for CI/VI.Rex Zhu2016-10-271-0/+18
* drm/amdgpu: rework IP block registration (v2)Alex Deucher2016-10-251-1/+10
* drm/amdgpu: move align_mask and nop into ring funcs as well (v2)Christian König2016-10-251-2/+3
* drm/amdgpu: move the ring type into the funcs structure (v2)Christian König2016-10-251-1/+2
* drm/amdgpu: move IB and frame size directly into the engine descriptionChristian König2016-10-251-16/+5
* drm/amdgpu/uvd5: add ring callbacks for ib and dma frame sizeAlex Deucher2016-09-161-0/+16
* drm/amdgpu: switch UVD code to use UVD_NO_OP for paddingAlex Deucher2016-08-241-1/+1
* drm/amdgpu: move UVD IB test into common code v2Christian König2016-07-291-44/+1
* drm/amdgpu: use begin/end_use for UVD power/clock gatingChristian König2016-07-291-0/+2
* drm/amdgpu: implement HDP functions for UVD v2Christian König2016-07-071-0/+29
* drm/amdgpu: move VM fields into jobChristian König2016-05-111-1/+2
* drm/amdgpu: move context switch handling into common code v2Christian König2016-05-111-1/+1
* drm/amd/amdgpu: Add name field to amd_ip_funcs (v2)Tom St Denis2016-05-111-0/+1
* drm/amd/amdgpu: Drop print_status callbacks.Tom St Denis2016-05-041-115/+0
* drm/amdgpu: use max_dw in ring_initChristian König2016-05-041-1/+1
* drm/amdgpu: handle more than 10 UVD sessions (v2)Arindam Nath2016-05-041-2/+3
* drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6Tom St Denis2016-05-021-0/+115
* drm/amdgpu: save and restore UVD context with suspend and resumeLeo Liu2016-04-041-2/+2
* Merge drm-fixes into drm-next.Dave Airlie2016-03-141-0/+8
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| * drma/dmgpu: move cg and pg flags into shared headersAlex Deucher2016-02-081-2/+2
| * drm/amdgpu: be consistent with uvd cg flagsAlex Deucher2016-02-081-0/+5
| * drm/amdgpu: handle uvd pg flags properlyAlex Deucher2016-02-081-0/+3
* | drm/amdgpu/vi: move uvd tiling config setup into uvd codeAlex Deucher2016-02-121-0/+10
* | drm/amdgpu: send UVD IB tests directly to the ring againChristian König2016-02-101-1/+1
* | drm/amdgpu: make pad_ib a ring function v3Christian König2016-02-101-0/+1
* | drm/amdgpu: remove the ring lock v2Christian König2016-02-101-4/+4
* | drm/amdgpu: remove some more semaphore leftoversAlex Deucher2016-02-101-1/+0
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