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| * | drm/amd/display: sspl: cleanup filter codeSamson Tam2025-02-126-590/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why & How] Remove unused filters and functions Add static to limit scope Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Make dcn401_program_pipe non staticAurabindo Pillai2025-02-122-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow reuse of code by making dcn401_program_pipe() non static. Fixes: 2739bd123782 ("drm/amd/display: Allow reuse of of DCN4x code") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: pass calculated dram_speed_mts to dml2Charlene Liu2025-02-123-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] currently dml2 is using a hard coded 16 to convert memclk to dram_speed_mts. for apu, this depends on wck_ratio. change to pass the already calculated dram_speed_mts from fpu to dml2. v2: use existing calculation of dram_speed_mts for now to avoid regression Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: add workaround flag to link to force FFE presetBrendan Tam2025-02-122-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There have been instances of some monitors being unable to link train on their reported link speed using their selected FFE preset. If a different FFE preset is found that has a higher rate of success during link training this workaround can be used to force its FFE preset. [How] A new link workaround flag is made called force_dp_ffe_preset. The flag is checked in override_training_settings and will set lt_settings->ffe_preset which is null if the flag is not set. The flag is then set in override_lane_settings. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Brendan Tam <Brendan.Tam@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: add s1_12 filter tablesSamson Tam2025-02-124-109/+1079
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why & How] Instead of converting tables from s1_10 to s1_12, add s1_12 tables instead. Remove init calls that do the conversion. Add APIs to read s1_10 tables Reviewed-by: Navid Assadian <navid.assadian@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: limit coverage of optimization skipAusef Yousof2025-02-123-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why&how] causing some regression on dgpu which still needs the pre-emptive return, limit this to reporter asic version it is simple to include different dcn versions from this point forward, each dcn resource is initialized with the flag and can be enabled at will Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Ausef Yousof <Ausef.Yousof@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: add new IRQ enum for underflowsLeo Zeng2025-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY & HOW] needed in certain scenarios for debugging and logging Reviewed-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Leo Zeng <Leo.Zeng@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: remove TF check for LLS policySamson Tam2025-02-121-24/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why & How] LLS policy not affected by TF. Remove check in don't care case and use pixel format only. Reviewed-by: Navid Assadian <navid.assadian@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: use s1_12 filter tables in SPLSamson Tam2025-02-121-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why & How] Instead of converting tables from s1_10 to s1_12, added s1_12 tables instead in SPL Remove init calls that do the conversion Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: DML21 ReintegrationAustin Zheng2025-02-1216-12853/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For various fixes to mcache_row_bytes calculation. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Don't try AUX transactions on disconnected linkIlya Bakoulin2025-02-121-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Setting link DPMS off in response to HPD disconnect creates AUX transactions on a link that is supposed to be disconnected. This can cause issues in some cases when the sink re-asserts HPD and expects source to re-enable the link. [How] Avoid AUX transactions on disconnected link. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: docstring definitions MAX_SURFACES and MAX_PLANESZaeem Mohamed2025-02-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MAX_SURFACES and MAX_PLANES now have docstrings that better show the difference between the two. Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Expose 3 secondary planes for supported ASICsZaeem Mohamed2025-02-124-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] For enabling 4-plane MPO, we need dc to expose 4 planes for DCN35 and beyond, as well as DCN21 [how] Set dc_caps.max_slave_*planes to 3 for appropriate ASICs Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 DM SupportWayne Lin2025-02-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Add DM handling for DCN36. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 COREWayne Lin2025-02-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DCN36 support in dc_resource.c. Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Support DCN36 HDCPWayne Lin2025-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add case in hdcp_create_workqueue() to support HDCP on DCN36 as well. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Support DCN36 DSCWayne Lin2025-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add case on clean_up_dsc_blocks() to support DCN36 as well. Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 DMCUBWayne Lin2025-02-124-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DMCU-B (Display Micro-Controller Unit B) is a display microcontroller used for shared display functionality with BIOS and for advanced power saving display features. Add case to support DCN3.6 as well. V2: adjust copyright license text Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 DML2 supportWayne Lin2025-02-124-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable DML2 for DCN36. Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 GPIOWayne Lin2025-02-122-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DCN36 support in GPIO. Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 ResourceWayne Lin2025-02-123-0/+2252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add resource handling for DCN36. V2: adjust copyright license text V3: remove unnecessary headers Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 IRQWayne Lin2025-02-123-0/+429
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IRQ services for DCN36. This allows us to create/init and manage irqs for DCN3 V2: adjust copyright license text Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 BIOS command table supportWayne Lin2025-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add case for DCN36 in command_table_helper2.c. Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DCN36 version identifiersWayne Lin2025-02-124-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DCN3.6 asic identifiers. Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Replace pr_info in dc_validate_boot_timing()Alex Hung2025-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use DC_LOG_DEBUG instead of pr_info to match other uses in dc.c. Fixes: 091e301c2b41 ("drm/amd/display: Add debug messages for dc_validate_boot_timing()") Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Remove unused link_enc_cfg_get_link_enc_used_by_streamDr. David Alan Gilbert2025-02-122-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | link_enc_cfg_get_link_enc_used_by_stream() is no longer used after 2021's: commit 6366b00346c0 ("drm/amd/display: Maintain consistent mode of operation during encoder assignment") which introduces and uses the _current version instead. Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Remove unused get_max_support_fbc_buffersizeDr. David Alan Gilbert2025-02-122-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_max_support_fbc_buffersize() is unused since 2021's commit 94f0d0c80cf3 ("drm/amd/display/dc/dce110/dce110_compressor: Remove unused function 'dce110_get_required_compressed_surfacesize") removed it's only caller. Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Remove unused hubbub1_toggle_watermark_change_reqDr. David Alan Gilbert2025-02-122-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hubbub1_toggle_watermark_change_req() last use was removed in 2017 by commit b8fce2c9d773 ("drm/amd/display: Optimize programming front end") Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Remove unused get_clock_requirements_for_stateDr. David Alan Gilbert2025-02-122-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_clock_requirements_for_state() was added in 2018 by commit 8ab2180f96f5 ("drm/amd/display: Add function to fetch clock requirements") but never used. Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Remove unused dc_stream_get_crtc_positionDr. David Alan Gilbert2025-02-122-39/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last user of dc_stream_get_crtc_position() was mod_freesync_get_v_position() which is removed in a previous patch in this series. Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Remove unused freesync functionsDr. David Alan Gilbert2025-02-122-163/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mod_freesync_get_vmin_vmax() and mod_freesync_get_v_position() were added in 2017 by commit 72ada5f76939 ("drm/amd/display: FreeSync Auto Sweep Support") mod_freesync_is_valid_range() was added in 2018 by commit e80e94460841 ("drm/amd/display: add method to check for supported range") mod_freesync_get_settings() was added in 2018 by commit a3e1737ed61c ("drm/amd/display: Implement stats logging") and mod_freesync_calc_field_rate_from_timing() was added in 2020 by commit 49c70ece54b0 ("drm/amd/display: Change input parameter for set_drr") None of these have been used. Remove them. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Remove unused mpc1_is_mpcc_idleDr. David Alan Gilbert2025-02-122-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mpc1_is_mpcc_idle() was added in 2017 by commit feb4a3cd8eb0 ("drm/amd/display: Integrating MPC pseudocode") but never used. Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: 3.2.319Taimur Hassan2025-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move SPL to a new path - Request HW cursor on DCN3.2 with SubVP - Allow reuse of of DCN4x code - Enable odm 4:1 when debug key is set - Fix seamless boot sequence - Support multiple options during psr entry. - Revert "Exit idle optimizations before attempt to access PHY" - Fix out-of-bound accesses - Fixes for mcache programming in DML21 Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Move SPL to a new pathSamson Tam2025-02-1227-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY & HOW] - Move SPL from dc/spl to dc/sspl - Update build files and header paths - Remove dc/spl files Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Request HW cursor on DCN3.2 with SubVPAric Cyr2025-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] When SubVP is active the HW cursor size is limited to 64x64, and anything larger will force composition which is bad for gaming on DCN3.2 if the game uses a larger cursor. [HOW] If HW cursor is requested, typically by a fullscreen game, do not enable SubVP so that up to 256x256 cursor sizes are available for DCN3.2. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Aric Cyr <Aric.Cyr@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Allow reuse of of DCN4x codeDmytro2025-02-1226-68/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the static qualifier to make it available for code sharing with other components. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Dmytro <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Enable odm 4:1 when debug key is setMuhammad Ahmed2025-02-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHAT] odm 4to1 is enabled when debug key is set. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Muhammad Ahmed <muhammad.ahmed@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Support multiple options during psr entry.Martin Tsai2025-02-123-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] Some panels may not handle idle pattern properly during PSR entry. [HOW] Add a condition to allow multiple options on power down sequence during PSR1 entry. Reviewed-by: Anthony Koo <anthony.koo@amd.com> Signed-off-by: Martin Tsai <Martin.Tsai@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | Revert "drm/amd/display: Exit idle optimizations before attempt to access PHY"Brandon Syu2025-02-121-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit de612738e9771bd66aeb20044486c457c512f684. Reason to revert: screen flashes or gray screen appeared half of the screen after resume from S4/S5. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Brandon Syu <Brandon.Syu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Fixes for mcache programming in DML21Dillon Varone2025-02-127-10/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY & HOW] - Fix indexing phantom planes for mcache programming in the wrapper - Fix phantom mcache allocations to align with HW guidance - Fix mcache assignment for chroma plane for multi-planar formats Reviewed-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: 3.2.318Aric Cyr2025-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version brings along the following fixes: - Fixes on psr_version, dcn35 register address, DCPG OP control sequences - Imporvements to CR AUX RD interval interpretation, dio link encoder - Disable PSR-SU on some OLED panels Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: refactor dio link encoder assigningPeichen Huang2025-02-124-3/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] We would like to have new dio encoder assigning flow. Which should be aligned with hpo assigning and have simple logic and data representation. [HOW} 1. A new config option to enable/disable the new code. 2. Encoder-link mapping is in res_ctx and assigned encoder. is accessed through pipe_ctx. 3. assign dio encoder when add stream to ctx Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Guard Possible Null Pointer DereferenceSung Lee2025-02-121-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] In some situations, dc->res_pool may be null. [HOW] Check if pointer is null before dereference. Reviewed-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Sung Lee <Sung.Lee@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add boot option to reduce PHY SSC for HBR3Hansen Dsouza2025-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Spread on DPREFCLK by 0.3 percent can have a negative effect on sink when PHY SSC is also spread by 0.3 percent [How] Add boot option for DMU to lower PHY SSC Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Ammend DCPG IP control sequences to align with HW guidanceDillon Varone2025-02-124-5/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY&HOW] IP_REQUEST_CNTL should only be toggled off when it was originally, never unconditionally. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Disable PSR-SU on some OLED panelTom Chung2025-02-121-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] PSR-SU may cause some glitching randomly on some OLED panel. [How] Disable the PSR-SU for certain PSR-SU OLED panel. Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Account For OTO Prefetch Bandwidth When Calculating Urgent ↵Austin Zheng2025-02-122-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bandwidth [Why] 1) The current calculations for OTO prefetch bandwidth do not consider the number of DPP pipes in use. As a result, OTO prefetch bandwidth may be larger than the vactive bandwidth if multiple DPP pipes are used. OTO prefetch bandwidth should never exceed the vactive bandwidth. 2) Mode programming may be mismatched with mode support In cases where mode support has chosen to use the equalized (equ) prefetch schedule, mode programming may end up using oto prefetch schedule instead. The bandwidth required to do the oto schedule may end up being higher than the equ schedule. This can cause the required urgent bandwidth to exceed the available urgent bandwidth. [How] Output the oto prefetch bandwidth and incorperate it into the urgent bandwidth calculations even if the prefetch schedule being used is not the oto schedule. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Update Cursor request mode to the beginning prefetch alwaysZhikai Zhai2025-02-122-14/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The double buffer cursor registers is updated by the cursor vupdate event. There is a gap between vupdate and cursor data fetch if cursor fetch data reletive to cursor position. Cursor corruption will happen if we update the cursor surface in this gap. [How] Modify the cursor request mode to the beginning prefetch always and avoid wraparound calculation issues. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Update CR AUX RD interval interpretationGeorge Shen2025-02-121-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] DP spec updated to have the CR AUX RD interval match the EQ AUX RD interval interpretation of DPCD 0000Eh/0220Eh for 8b/10b non-LTTPR mode and LTTPR transparent mode cases. [How] Update interpretation of DPCD 0000Eh/0220Eh for CR AUX RD interval during 8b/10b link training. Reviewed-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Initial psr_version with correct settingTom Chung2025-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why & How] The initial setting for psr_version is not correct while create a virtual link. The default psr_version should be DC_PSR_VERSION_UNSUPPORTED. Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-26 11:52:18 +0000