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path: root/drivers/gpu/drm/i915/display/intel_cdclk.c
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* drm/i915/display/adl_p: Implement Wa_22011320316José Roberto de Souza2021-05-141-1/+20
* drm/i915: Move intel_modeset_all_pipes()Ville Syrjälä2021-05-141-38/+0
* drm/i915/adl_p: Add cdclk support for ADL-PAnusha Srivatsa2021-05-141-13/+28
* drm/i915: Use intel_de_wait_for_*() in cnl+ cdclk programmingVille Syrjälä2021-05-051-6/+4
* drm/i915: Use intel_de_rmw() in bxt/glk/cnl+ cdclk programmingVille Syrjälä2021-05-051-10/+4
* drm/i915: Use intel_de_rmw() in skl cdclk programmingVille Syrjälä2021-05-051-14/+11
* drm/i915: Use intel_de_rmw() in bdw cdclk programmingVille Syrjälä2021-05-051-11/+6
* drm/i915: Extract some helpers to compute cdclk register valuesVille Syrjälä2021-05-051-98/+88
* drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä2021-05-051-0/+1
* drm/i915/display: rename display version macrosLucas De Marchi2021-04-141-9/+9
* drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper2021-04-141-16/+18
* drm/i915/display: Simplify GLK display version testsMatt Roper2021-03-231-12/+14
* drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper2021-03-231-29/+29
* drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGEMatt Roper2021-03-231-2/+2
* drm/i915: Index min_{cdclk,voltage_level}[] with pipeVille Syrjälä2021-02-051-4/+4
* drm/i915: Remove references to struct drm_device.pdevThomas Zimmermann2021-02-021-7/+7
* drm/i915: Add intel_atomic_add_affected_planes()Ville Syrjälä2020-12-041-2/+1
* drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()Jani Nikula2020-12-011-2/+2
* drm/i915/rkl: Add new cdclk tableMatt Roper2020-10-161-1/+31
* drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay2020-10-141-2/+2
* drm/i915/dg1: Initialize RAWCLK properlyMatt Roper2020-10-071-1/+15
* drm/i915: Nuke force_min_cdclk_changedVille Syrjälä2020-09-171-1/+1
* Merge tag 'v5.9-rc4' into drm-nextDave Airlie2020-09-081-5/+5
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| * treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-08-231-5/+5
* | drm/i915: Make i830 .get_cdclk() assignment less confusingVille Syrjälä2020-08-171-4/+5
* | drm/i915: Fix some whitespaceVille Syrjälä2020-08-171-1/+1
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* drm/i915/tgl: Clamp min_cdclk to max_cdclk_freq to unblock 8KStanislav Lisovskiy2020-07-031-2/+9
* Revert "drm/i915: Remove unneeded hack now for CDCLK"Stanislav Lisovskiy2020-06-081-0/+12
* drm/i915: Fix wrong CDCLK adjustment changesStanislav Lisovskiy2020-06-041-8/+11
* drm/i915: Fix includes and local vars orderStanislav Lisovskiy2020-05-221-1/+2
* drm/i915: Remove unneeded hack now for CDCLKStanislav Lisovskiy2020-05-211-12/+0
* drm/i915: Adjust CDCLK accordingly to our DBuf bw needsStanislav Lisovskiy2020-05-211-4/+24
* drm/i915: Read out hrawclk on all gen3+ platformsVille Syrjälä2020-05-191-24/+40
* drm/i915: Document our lackluster FSB frequency readoutVille Syrjälä2020-05-191-1/+10
* drm/i915: Fix 400 MHz FSB readout on elkVille Syrjälä2020-05-191-2/+7
* drm/i915: Lock gmbus/aux mutexes while changing cdclkVille Syrjälä2020-03-091-0/+22
* drm/i915/display/cdclk: Make WARN* drm specific where drm_priv ptr is availablePankaj Bharadiya2020-02-231-36/+48
* drm/i915: Read rawclk_freq earlierChris Wilson2020-02-191-9/+10
* drm/i915: Fix the docs for intel_set_cdclk_post_plane_update()Ville Syrjälä2020-02-111-1/+1
* drm/i915/tgl: Update cdclk voltage level settingsMatt Roper2020-02-101-1/+18
* drm/i915: Store active_pipes bitmask in cdclk stateVille Syrjälä2020-01-311-9/+11
* drm/i915: Convert cdclk to global stateVille Syrjälä2020-01-311-83/+109
* drm/i915: Introduce better global state handlingVille Syrjälä2020-01-311-4/+4
* drm/i915: s/init_cdclk/init_cdclk_hw/Ville Syrjälä2020-01-311-12/+12
* drm/i915: swap() the entire cdclk stateVille Syrjälä2020-01-311-15/+3
* drm/i915: Extract intel_cdclk_stateVille Syrjälä2020-01-311-77/+91
* drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling conventionVille Syrjälä2020-01-311-22/+22
* drm/i915: s/cdclk_state/cdclk_config/Ville Syrjälä2020-01-311-211/+215
* drm/i915: s/need_cd2x_updare/can_cd2x_update/Ville Syrjälä2020-01-311-7/+7
* drm/i915: Collect more cdclk state under the same roofVille Syrjälä2020-01-311-14/+26
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