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path: root/drivers/gpu/drm/i915/display
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| * | | drm/i915/audio: Use REG_BIT() & co.Ville Syrjälä2022-10-272-51/+45
| * | | drm/i915/audio: Extract struct ilk_audio_regsVille Syrjälä2022-10-271-42/+43
| * | | drm/i915/audio: Remove CL/BLC audio stuffVille Syrjälä2022-10-272-25/+6
| * | | drm/i915/audio: Nuke leftover ROUNDING_FACTORVille Syrjälä2022-10-271-2/+0
| * | | drm/i915/audio: s/dev_priv/i915/Ville Syrjälä2022-10-272-197/+196
| * | | drm/i915/display: Move squash_ctl register programming to its own functionAnusha Srivatsa2022-10-261-9/+14
| * | | drm/i915/display: Move chunks of code out of bxt_set_cdclk()Anusha Srivatsa2022-10-261-15/+24
| * | | drm/i915/display: Introduce HAS_CDCLK_SQUASH macroAnusha Srivatsa2022-10-261-10/+5
| * | | drm/i915/display: Change terminology for cdclk actionsAnusha Srivatsa2022-10-261-8/+8
| * | | drm/i915/tgl+: Sanitize DKL PHY register definitionsImre Deak2022-10-266-152/+159
| * | | drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.hImre Deak2022-10-266-0/+198
| * | | drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.hImre Deak2022-10-264-6/+6
| * | | drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak2022-10-266-76/+199
| * | | drm/i915: Stop loading linear degamma LUT on glk needlesslyVille Syrjälä2022-10-261-23/+3
| * | | drm/i915: Get rid of glk_load_degamma_lut_linear()Ville Syrjälä2022-10-265-42/+82
| * | | drm/i915: Assert {pre,post}_csc_lut were assigned sensiblyVille Syrjälä2022-10-263-0/+23
| * | | drm/i915: Introduce crtc_state->{pre,post}_csc_lutVille Syrjälä2022-10-266-57/+114
| * | | drm/i915: Make ilk_load_luts() deal with degammaVille Syrjälä2022-10-261-2/+4
| * | | drm/i915: Introduce intel_crtc_needs_color_update()Ville Syrjälä2022-10-224-19/+16
| * | | drm/i915: Don't flag both full modeset and fastset at the same timeVille Syrjälä2022-10-221-1/+8
| * | | drm/i915: Remove some local 'mode_changed' boolsVille Syrjälä2022-10-221-8/+6
| * | | drm/i915: Introduce intel_crtc_needs_fastset()Ville Syrjälä2022-10-227-21/+33
| * | | drm/i915: Activate DRRS after state readoutVille Syrjälä2022-10-221-36/+7
| * | | drm/i915: Allow panel fixed modes to have differing sync polaritiesVille Syrjälä2022-10-211-3/+4
| * | | drm/i915: Remove one use macroSuraj Kandpal2022-10-212-8/+12
| * | | drm/i915/dp: Remove whitespace at the end of function.Ankit Nautiyal2022-10-201-1/+0
| * | | drm/i915/dp: Reset frl trained flag before restarting FRL trainingAnkit Nautiyal2022-10-201-0/+2
| * | | drm/i915: Print return value on errorNirmoy Das2022-10-191-3/+3
| * | | drm/i915: Fix simulated GPU reset wrt. encoder HW readoutImre Deak2022-10-141-7/+17
| * | | drm/i915/display: Add DC5 counter and DMC debugfs entries for MTLAnusha Srivatsa2022-10-111-12/+10
| * | | drm/i915: use proper helper for register updatesAndrzej Hajda2022-10-111-7/+2
| * | | drm/i915/display: remove drm_device aliasesAndrzej Hajda2022-10-1113-92/+66
| * | | drm/i915: Write watermarks for disabled pipes on gmch platformsVille Syrjälä2022-10-071-3/+1
| * | | drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platformsVille Syrjälä2022-10-071-0/+4
| * | | drm/i915: Fix g4x/vlv/chv CxSR vs. format/tiling/rotation changesVille Syrjälä2022-10-071-8/+45
| * | | drm/i915: Clean up some namespacingVille Syrjälä2022-10-075-7/+7
| * | | drm/i915/mtl: Add MTP ddc pin configurationRadhakrishna Sripada2022-10-051-1/+1
| * | | drm/i915/mtl: Extend PSR supportJosé Roberto de Souza2022-10-041-11/+20
| * | | drm/i915: Setup final panel drrs_type already during initVille Syrjälä2022-10-041-3/+3
| * | | drm/i915: Tighten DRRS capability reportingVille Syrjälä2022-10-041-2/+17
| * | | drm/i915: Fix locking in DRRS debugfsVille Syrjälä2022-10-031-2/+10
| * | | drm/i915: Make DRRS debugfs per-crtc/connectorVille Syrjälä2022-10-033-72/+69
| * | | drm/i915: Make the DRRS debugfs contents more consistentVille Syrjälä2022-10-031-5/+5
| * | | drm/i915: Move DRRS debugfs next to the implementationVille Syrjälä2022-10-033-95/+108
| * | | drm/i915: Reject excessive dotclocks earlyVille Syrjälä2022-10-031-0/+18
| * | | drm/i915: Simplify modifier lookup in watermark codeVille Syrjälä2022-10-033-19/+17
| * | | drm/i915: Fix watermark calculations for DG2 CCS+CC modifierVille Syrjälä2022-10-031-2/+4
| * | | drm/i915: Fix watermark calculations for DG2 CCS modifiersVille Syrjälä2022-10-031-2/+6
| * | | drm/i915: Fix watermark calculations for gen12+ CCS+CC modifierVille Syrjälä2022-10-031-2/+4
| * | | drm/i915: Fix watermark calculations for gen12+ MC CCS modifierVille Syrjälä2022-10-031-2/+4
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