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path: root/drivers/gpu/drm/i915/gvt/handlers.c
Commit message (Expand)AuthorAgeFilesLines
* Backmerge tag 'v4.11-rc6' into drm-nextDave Airlie2017-04-111-1/+9
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| * drm/i915/gvt: add write handler for mmio mbctlPei Zhang2017-03-201-1/+9
* | drm/i915/gvt: add some statistic routine for schedulerPing Gao2017-03-301-0/+1
* | drm/i915/gvt: Add KBL dispatch logic in each function.Xu Han2017-03-291-6/+13
* | drm/i915/gvt: Update MMIO handle policy to compatible KBL platform.Xu Han2017-03-291-198/+211
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* drm/i915/gvt: replace the gvt_err with gvt_vgpu_errTina Zhang2017-03-171-15/+13
* drm/i915/gvt: handle force-nonpriv registers, cmd parser partZhao Yan2017-03-171-0/+17
* drm/i915/gvt: fix an error for F_RO flagZhao Yan2017-03-021-0/+1
* drm/i915/gvt: fix an error for one registerZhao Yan2017-03-011-1/+1
* drm/i915/gvt: add more registers into handlers listZhao Yan2017-03-011-0/+22
* drm/i915/gvt: have more registers with F_CMD_ACCESS flags setZhao Yan2017-03-011-100/+123
* drm/i915/gvt: add some new MMIOs to cmd_access white listPei Zhang2017-02-241-2/+3
* drm/i915/gvt: fix pcode mailbox write emulation of BDWWeinan Li2017-02-241-15/+18
* drm/i915/gvt: refine pcode write emulationWeinan Li2017-02-231-2/+10
* drm/i915/gvt: add cmd_access to GEN7_HALF_SLICE_CHICKEN1Pei Zhang2017-02-231-1/+1
* drm/i915/gvt: force-nopriv register handlingZhao Yan2017-02-231-4/+70
* drm/i915/gvt: Fix superfluous newline in GVT_DISPLAY_READY env varTakashi Iwai2017-02-231-1/+1
* drm/i915/gvt: fix unhandled mmio warningsZhao Yan2017-02-231-4/+11
* drm/i915/gvt: enter failsafe mode when guest requires more resourcesMin He2017-02-231-0/+5
* drm/i915/gvt: handle fence reg access during GPU resetZhao, Xinda2017-02-171-6/+9
* drm/i915/gvt: introduced failsafe mode into vgpuMin He2017-02-171-0/+36
* Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torval...Dave Airlie2017-01-271-68/+35
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| * drm/i915/gvt: rewrite gt reset handler using new function intel_gvt_reset_vgp...Changbin Du2017-01-131-61/+29
| * drm/i915/gvt: move mmio init/clean function to mmio.cChangbin Du2017-01-131-1/+1
| * drm/i915/gvt: fix return value in mul_force_wake_writeChangbin Du2017-01-091-1/+1
| * drm/i915/gvt: fix error handing of tlb_control emulationChangbin Du2017-01-091-4/+2
| * drm/i915/gvt: verify functions types in new_mmio_info()Nicolas Iooss2017-01-091-2/+3
* | drm/i915: rename OACONTROL GEN7_OACONTROLRobert Bragg2016-11-221-1/+1
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* drm/i915/gvt: drop checks for early Skylake revisionsJani Nikula2016-11-171-4/+2
* drm/i915/gvt: add more MMIO regs with command access flagPing Gao2016-11-141-14/+16
* drm/i915/gvt: emulate right behavior for tlb_controlPing Gao2016-11-141-0/+1
* drm/i915/gvt: emulate vgpu engine reset control behaviorDu, Changbin2016-11-071-0/+26
* drm/i915/gvt: update misc ctl regs base on stepping infoPing Gao2016-11-071-5/+6
* drm/i915/gvt: correct the emulation in TLB control handlerPing Gao2016-11-071-0/+2
* drm/i915/gvt: add write vreg in MMIO DMA_CTRL handlerPing Gao2016-11-071-1/+4
* drm/i915/gvt: throw error basing on execlist submit resultBing Niu2016-10-271-3/+6
* drm/i915/gvt: add full vGPU reset supportPing Gao2016-10-271-0/+10
* drm/i915/gvt: correct the reset logicPing Gao2016-10-261-1/+5
* drm/i915/gvt: add vreg write for GDRST handlerPing Gao2016-10-261-0/+1
* drm/i915/gvt: properly access enabled intel_engine_csZhenyu Wang2016-10-201-5/+6
* drm/i915/gvt: clean up intel_gvt.h as interface for i915 coreZhenyu Wang2016-10-201-0/+2
* drm/i915/gvt: Fix build failure after intel_engine_cs changeZhenyu Wang2016-10-181-1/+1
* drm/i915/gvt: vGPU context switchZhi Wang2016-10-141-5/+36
* drm/i915/gvt: vGPU schedule policy frameworkZhi Wang2016-10-141-2/+25
* drm/i915/gvt: vGPU workload schedulerZhi Wang2016-10-141-2/+23
* drm/i915/gvt: vGPU workload submissionZhi Wang2016-10-141-2/+36
* drm/i915/gvt: vGPU display virtualizationZhi Wang2016-10-141-114/+977
* drm/i915/gvt: vGPU MMIO virtualizationZhi Wang2016-10-141-4/+1579
* drm/i915/gvt: Introduce a framework for tracking HW registers.Zhi Wang2016-10-141-0/+247
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