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path: root/drivers/gpu/drm/i915/i915_gem_tiling.c
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* drm/i915: fix tiling limits for i915 class hw v2Daniel Vetter2010-04-181-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code is definitely crap: Largest pitch allowed spills into the TILING_Y bit of the fence registers ... :( I've rewritten the limits check under the assumption that 3rd gen hw has a 3d pitch limit of 8kb (like 2nd gen). This is supported by an otherwise totally misleading XXX comment. This bug mostly resulted in tiling-corrupted pixmaps because the kernel allowed too wide buffers to be tiled. Bug brought to the light by the xf86-video-intel 2.11 release because that unconditionally enabled tiling for pixmaps, relying on the kernel to check things. Tiling for the framebuffer was not affected because the ddx does some additional checks there ensure the buffer is within hw-limits. v2: Instead of computing the value that would be written into the hw fence registers and then checking the limits simply check whether the stride is above the 8kb limit. To better document the hw, add some WARN_ONs in i915_write_fence_reg like I've done for the i830 case (using the right limits). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27449 Tested-by: Alexander Lam <lambchop468@gmail.com> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: introduce to_intel_bo helperDaniel Vetter2010-03-251-5/+5
| | | | | | | | | | | | | | This is a purely cosmetic change to make changes in this area easier. And hey, it's not only clearer and typechecked, but actually shorter, too! [anholt: To clarify, this is a change to let us later make drm_i915_gem_object subclass drm_gem_object, instead of having drm_gem_object have a pointer to i915's private data] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/intel: fix up set_tiling for untiled->tiled transitionDaniel Vetter2010-03-181-2/+5
| | | | | | | | | | | | | | | | | | | | | | Bug introduced in commit 10ae9bd25acf394c8fa2f9d795dfa9cec4d19ed6 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Feb 1 13:59:17 2010 +0100 drm/i915: blow away userspace mappings before fence change The problem is that when there's no fence reg assigned and the object is mapped at a fenceable offset in the gtt, the userspace mappings won't be torn down. Which happens on untiled->tiled transition quite often on 4th gen and later because there fencing does not have any special alignment constraints (as opposed to 2nd and 3rd gen on which I've tested the original commit). Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=26993 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Tested-by: Eric Anholt <eric@anholt.net> (fixes OpenArena) Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.Eric Anholt2010-02-261-1/+1
| | | | Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge remote branch 'anholt/drm-intel-next' into drm-next-stageDave Airlie2010-02-251-162/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * anholt/drm-intel-next: drm/i915: Record batch buffer following GPU error drm/i915: give up on 8xx lid status drm/i915: reduce some of the duplication of tiling checking drm/i915: blow away userspace mappings before fence change drm/i915: move a gtt flush to the correct place agp/intel: official names for Pineview and Ironlake drm/i915: overlay: drop superflous gpu flushes drm/i915: overlay: nuke readback to flush wc caches drm/i915: provide self-refresh status in debugfs drm/i915: provide FBC status in debugfs drm/i915: fix drps disable so unload & re-load works drm/i915: Fix OGLC performance regression on 945 drm/i915: Deobfuscate the render p-state obfuscation drm/i915: add dynamic performance control support for Ironlake drm/i915: enable memory self refresh on 9xx drm/i915: Don't reserve compatibility fence regs in KMS mode. drm/i915: Keep MCHBAR always enabled drm/i915: Replace open-coded eviction in i915_gem_idle()
| * drm/i915: reduce some of the duplication of tiling checkingOwain Ainsworth2010-02-221-34/+1
| | | | | | | | | | | | | | | | | | | | i915_gem_object_fenceable was mostly just a repeat of the i915_gem_object_fence_offset_ok, but also checking the size (which was checkecd when we allowed that BO to be tiled in the first place). So instead, export the latter function and use it in place. Signed-Off-By: Owain G. Ainsworth <oga@openbsd.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: blow away userspace mappings before fence changeDaniel Vetter2010-02-221-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | This aligns it with the other user of i915_gem_clear_fence_reg, which blows away the mapping before changing the fence reg. Only affects userspace if it races against itself when changing tiling parameters, i.e. behaviour is undefined, anyway. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Keep MCHBAR always enabledZhenyu Wang2010-02-161-122/+0
| | | | | | | | | | | | | | | | | | As we need more and more controls within MCHBAR for memory config and power management, this trys to keep MCHBAR enabled from driver load and only tear down in driver unload. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | Use drm_gem_object_[handle_]unreference_unlocked where possibleLuca Barbieri2010-02-111-3/+1
|/ | | | | | | | | | | Mostly obvious simplifications. The i915 pread/pwrite ioctls, intel_overlay_put_image and nouveau_gem_new were incorrectly using the locked versions without locking: this is also fixed in this patch. Signed-off-by: Luca Barbieri <luca@luca-barbieri.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915: execbuf2 supportJesse Barnes2010-01-061-24/+22
| | | | | | | | | | | | | | | | | | | This patch adds a new execbuf ioctl, execbuf2, for use by clients that want to control fence register allocation more finely. The buffer passed in to the new ioctl includes a new relocation type to indicate whether a given object needs a fence register assigned for the command buffer in question. Compatibility with the existing execbuf ioctl is implemented in terms of the new code, preserving the assumption that fence registers are required for pre-965 rendering commands. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: Remove pre-emptive clear_fence_reg()] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> [anholt: Removed dmesg spam] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix product names and #definesAdam Jackson2009-12-071-2/+2
| | | | | | | | | IGD* isn't a useful name. Replace with the codenames, as sourced from pci.ids. Signed-off-by: Adam Jackson <ajax@redhat.com> [anholt: Fixed up for merge with pineview/ironlake changes] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Replace DRM_DEBUG with DRM_DEBUG_DRIVERZhao Yakui2009-11-051-1/+1
| | | | | | | | | | | | Replace the DRM_DEBUG with DRM_DEBUG_DRIVER in generic i915 driver. Then the debug info can be obtained by adding the boot option of "drm.debug=0x02". At the same time the debug info in increase/decrease clock is also printed by using DRM_DEBUG_DRIVER instead of DRM_DEBUG_KMS. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: get the bridge device once.Dave Airlie2009-09-081-45/+20
| | | | | | | | | The driver gets the bridge device in a number of places, upcoming vga arb code paths need the bridge device, however they need it in under a lock, and the pci lookup can allocate memory. So clean this code up before then and get the bridge once for the driver lifetime. Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915: fix tiling on IGDNGZhenyu Wang2009-09-041-8/+7
| | | | | | | | | | | | | It seems that on IGDNG the same swizzling setup always applys. And front buffer tiling needs to set address swizzle in display arb control too. Fix plane tricle feed setting in v1 which should be disable bit, and always setup address swizzle to let hardware care for buffer tiling in all cases. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Zap the GTT mapping when transitioning from untiled to tiled.Eric Anholt2009-07-101-0/+6
| | | | | | | | As of 52dc7d32b88156248167864f77a9026abe27b432, we could leave an old linear GTT mapping in place, so that apps trying to GTT-mapped write in tiled data wouldn't get the fence added, and garbage would get displayed. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: check for CONFIG_PNP before using pnp functionKeith Packard2009-06-181-0/+2
| | | | Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: Clear fence register on tiling stride change.Chris Wilson2009-06-181-16/+51
| | | | | | | | | | The fence register value also depends upon the stride of the object, so we need to clear the fence if that is changed as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [anholt: Added 8xx and 965 paths, and renamed the confusing i915_gem_object_tiling_ok function to i915_gem_object_fence_offset_ok] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: enable MCHBAR if neededJesse Barnes2009-06-091-0/+145
| | | | | | | | | | | | | | | Using the new PNP resource checking code, this patch allows the i915 driver to allocate MCHBAR space if needed and use the BAR to determine current memory settings. [apw@canonical.com: moved to the new generic PNP resource interface] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Andy Whitcroft <apw@canonical.com> Signed-off-by: Eric Anholt <eric@anholt.net> failure to update-index after git-am --reject to hand-apply Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Disable tiling on IGDNG for nowZhenyu Wang2009-06-051-0/+7
| | | | | | | Swizzle bit detection not working right on it. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix tiling pitch handling on 8xx.Eric Anholt2009-05-261-3/+11
| | | | | | | | | | | | | The pitch field is an exponent on pre-965, so we were rejecting buffers on 8xx that we shouldn't have. 915 got lucky in that the largest legal value happened to match (8KB / 512 = 0x10), but 8xx has a smaller tile width. Additionally, we programmed that bad value into the register on 8xx, so the only pitch that would work correctly was 4096 (512-1023 pixels), while others would probably give bad rendering or hangs. Signed-off-by: Eric Anholt <eric@anholt.net> fd.o bug #20473.
* drm/i915: fix transition to I915_TILING_NONEKeith Packard2009-04-171-1/+0
| | | | | | | | | Transitions to TILING_NONE skipped the call to unbind the object, which left the fence register set and caused future CPU access through the GTT to access the object in tiled mode. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Allow tiling of objects with bit 17 swizzling by the CPU.Eric Anholt2009-04-081-2/+109
| | | | | | | | | | | | Save the bit 17 state of the pages when freeing the page list, and reswizzle them if necessary when rebinding the pages (in case they were swapped out). Since we have userland with expectations that the swizzle enums let it pread and pwrite contents accurately, we can't expose a new swizzle enum for bit 17 (which it would have to GTT map to handle), so we handle it down in pread and pwrite by swizzling the copy when bit 17 of the page address is set. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix up tiling/fence reg setup on i8xx class hwDaniel Vetter2009-04-011-0/+16
| | | | | | | | | | | | | | | | | | | This fixes all the tiling problems with the 2d ddx. glxgears still doesn't work. Changes: - fix a copy&paste error in i8xx fence reg setup. It resulted in an at most a 512KB offset of the fence reg window, so was only visible sometimes. - add tests for stride and object size constrains (also for i915 and 1965 class hw). Userspace seems to have an of-by-one bug there, which changes the fence size by at most 512KB due to an overflow. - because i8xx hw is quite old (and therefore not as well-tested) I left 2 debug WARN_ONs in the i8xx fence reg setup code to hopefully catch any further overflows in the bit-fields. Lastly there's one small change to make the alignment checks more consistent. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=20289 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Change DCC tiling detection case to cover only mobile parts.Eric Anholt2009-03-271-16/+15
| | | | | | | | | Later spec investigation has revealed that every 9xx mobile part has had this register in this format. Also, no non-mobile parts have been shown to have this register. So make all mobile use the same code, and all non-mobile use the hack 965 detection. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: hold mutex for unreference() in i915_gem_tiling.cChris Wilson2009-02-201-4/+2
| | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm/i915: Unref the object after failing to set tiling mode.Chris Wilson2009-02-081-1/+4
| | | | | | | | Cleanup the object reference on the error paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm/i915: add fence register management to execbufJesse Barnes2009-02-081-1/+87
| | | | | | | | | | | | Adds code to set up fence registers at execbuf time on pre-965 chips as necessary. Also fixes up a few bugs in the pre-965 tile register support (get_order != ffs). The number of fences available to the kernel defaults to the hw limit minus 3 (for legacy X front/back/depth), but a new parameter allows userspace to override that as needed. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm/i915: add GEM GTT mapping supportJesse Barnes2008-12-291-0/+1
| | | | | | | | | | Use the new core GEM object mapping code to allow GTT mapping of GEM objects on i915. The fault handler will make sure a fence register is allocated too, if the object in question is tiled. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915: Respect GM965/GM45 bit-17-instead-of-bit-11 option for swizzling.Eric Anholt2008-12-041-3/+4
| | | | | | | | | | | | | This fixes readpixels and buffer corruption when swapped out and in by disabling tiling on them. Now that we know that the bit 17 mode isn't just a mistake of older chipsets, we'll need to work on a clever fix so that we can get the performance of tiling on these chipsets, but that will require intrusive changes targeted at the next kernel release, not this one. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* i915: GM45 has GM965-style MCH setup.Eric Anholt2008-10-181-2/+3
| | | | | | | Fixes tiling swizzling mode failures that manifest in glReadPixels(). Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm: G33-class hardware has a newer 965-style MCH (no DCC register).Eric Anholt2008-10-181-1/+1
| | | | | | | | Fixes bad software fallback rendering in Mesa in dual-channel configurations. d9a2470012588dc5313a5ac8bb2f03575af00e99 Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm: Add GEM ("graphics execution manager") to i915 driver.Eric Anholt2008-10-181-0/+256
GEM allows the creation of persistent buffer objects accessible by the graphics device through new ioctls for managing execution of commands on the device. The userland API is almost entirely driver-specific to ensure that any driver building on this model can easily map the interface to individual driver requirements. GEM is used by the 2d driver for managing its internal state allocations and will be used for pixmap storage to reduce memory consumption and enable zero-copy GLX_EXT_texture_from_pixmap, and in the 3d driver is used to enable GL_EXT_framebuffer_object and GL_ARB_pixel_buffer_object. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
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