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path: root/drivers/gpu/drm/i915/i915_reg.h
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* | | | | | drm/i915/reg: fix QGV points register access offsetsVinod Govindapillai2023-03-271-2/+3
* | | | | | drm/i915: Move PLANE_BUG_CFG bit definitions to the correct placeVille Syrjälä2023-03-251-5/+5
* | | | | | drm/i915/dpt: Add a modparam to disable DPT via the chicken bitVille Syrjälä2023-03-241-0/+2
* | | | | | drm/i915: Add PLANE_CHICKEN registersVille Syrjälä2023-03-241-0/+9
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* | | | | drm/i915: Clean up skl+ plane alpha bitsVille Syrjälä2023-03-171-2/+3
* | | | | drm/i915: Define vlv/chv sprite plane SURFLIVE registersVille Syrjälä2023-03-171-0/+3
* | | | | drm/i915: Define skl+ universal plane SURFLIVE registersVille Syrjälä2023-03-171-0/+9
* | | | | drm/i915: Program VLV/CHV PIPE_MSA_MISC registerVille Syrjälä2023-03-171-0/+6
* | | | | drm/i915: Define more pipe timestamp registersVille Syrjälä2023-03-171-1/+17
* | | | | drm/i915: s/PIPEMISC/PIPE_MISC/Ville Syrjälä2023-03-171-17/+17
* | | | | drm/i915: Stop using pipe_offsets[] for PIPE_MISC*Ville Syrjälä2023-03-171-2/+2
* | | | | drm/i915/display/mtl: Program latch to phy resetJosé Roberto de Souza2023-03-091-0/+2
* | | | | drm/i915/mtl: Fix Wa_16015201720 implementationRadhakrishna Sripada2023-03-091-3/+5
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* | | | drm/i915: Get rid of the gm45 HPD live state nonsenseVille Syrjälä2023-03-071-12/+1
* | | | drm/i915/display: split out DSC and DSS registersJani Nikula2023-03-061-450/+0
* | | | drm/i915/dsb: Define more DSB registersVille Syrjälä2023-02-201-2/+48
* | | | drm/i915: Define transcoder timing register bitmasksVille Syrjälä2023-02-171-0/+24
* | | | drm/i915: Define the "unmodified vblank" interrupt bitVille Syrjälä2023-02-171-0/+1
* | | | drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä2023-02-171-53/+53
* | | | drm/i915: Give CPU transcoder timing registers TRANS_ prefixVille Syrjälä2023-02-171-46/+46
* | | | drm/i915/dgfx, mtl+: Disable display functionality if the display is not presentImre Deak2023-02-151-0/+3
* | | | drm/i915/lvds: Extract intel_lvds_regs.hVille Syrjälä2023-01-311-54/+0
* | | | drm/i915/lvds: Use REG_BIT() & co.Ville Syrjälä2023-01-311-24/+22
* | | | drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()Lucas De Marchi2023-01-271-4/+5
* | | | drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()Lucas De Marchi2023-01-271-3/+5
* | | | drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()Lucas De Marchi2023-01-271-7/+9
* | | | drm/i915: Convert pll macros to _PICK_EVEN_2RANGESLucas De Marchi2023-01-271-30/+29
* | | | drm/i915: Fix coding style on DPLL*_ENABLE definesLucas De Marchi2023-01-271-10/+10
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* | | Merge drm/drm-next into drm-intel-nextJani Nikula2023-01-251-0/+3
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| * | Merge tag 'drm-intel-gt-next-2023-01-18' of git://anongit.freedesktop.org/drm...Daniel Vetter2023-01-241-0/+3
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| | * Merge drm/drm-next into drm-intel-gt-nextRodrigo Vivi2022-12-301-99/+32
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| | * | drm/i915/gsc: Do a driver-FLR on unload if GSC was loadedDaniele Ceraolo Spurio2022-12-091-0/+3
* | | | drm/i915/psr: Implement Wa_14015648006Jouni Högander2023-01-171-0/+1
* | | | drm/i915/dsb: Stop with the RMWVille Syrjälä2023-01-131-1/+1
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* | | Merge drm/drm-next into drm-intel-nextJani Nikula2023-01-021-0/+10
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| * | Merge tag 'drm-intel-next-2022-11-18' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2022-11-231-99/+32
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| * | drm/i915/mtl: Add Wa_14017073508 for SAMediaBadal Nilawar2022-11-141-0/+9
| * | drm/i915/mtl: add initial definitions for GSC CSDaniele Ceraolo Spurio2022-11-071-0/+1
* | | drm/i915/dsi: add support for ICL+ native MIPI GPIO sequenceJani Nikula2022-12-201-0/+1
* | | drm/i915: Document LUT "max" register precisionVille Syrjälä2022-12-131-5/+5
* | | drm/i915: Clean up various indexed LUT registersVille Syrjälä2022-12-131-8/+10
* | | drm/i915: Define skl+ palette anti-collision bitVille Syrjälä2022-12-131-0/+1
* | | drm/i915: Clean up GAMMA_MODE definesVille Syrjälä2022-12-131-8/+8
* | | drm/i915: Shorten GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED a bitVille Syrjälä2022-12-131-1/+1
* | | drm/i915: Reject unusable power sequencersVille Syrjälä2022-12-091-0/+1
* | | drm/i915/dvo: Extract intel_dvo_regs.hVille Syrjälä2022-11-231-44/+0
* | | drm/i915/dvo: Use REG_BIT() & co. for DVO registersVille Syrjälä2022-11-231-30/+33
* | | drm/i915/dvo: Rename the "active data order" bitsVille Syrjälä2022-11-231-4/+4
* | | drm/i915/dvo: Define a few more DVO register bitsVille Syrjälä2022-11-231-1/+3
* | | drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registersVille Syrjälä2022-11-231-6/+5
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