| Commit message (Collapse) | Author | Age | Files | Lines |
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The TCNE2 bit of the DEFR6 register was renamed to TCNE1 in the R-Car gen2
manuals -- which makes more sense as that bit controls whether DU1, not DU2
is connected to TCON.
While at it, add the TCNE0 bit which controls whether DU0 is connected to
TCON.
Based on the large patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>.
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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Document the R8A7795-specific DT bindings and support them in the
driver. The HDMI and LVDS outputs are currently not supported.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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The ODDF signal, output by default on the ODDF pin, isn't used on any
board supported in the kernel. As the Gen3 Salvator-X board uses the
ODDF pin as a DISP signal, hardcode that configuration in the driver.
Use of the ODDF signal will be implemented later through proper DT-based
configuration of the DU pins.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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The Gen3 R8A7795 DU has 4 CRTCs, support them all.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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Configure the plane source at plane setup time to source frames from
memory or from the VSP1.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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Accept interlaced modes on the VGA and HDMI connectors and configure the
hardware accordingly.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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The DU uses the module functional clock as the default pixel clock, but
supports using an externally supplied pixel clock instead. Support this
by adding the external pixel clock to the DT bindings, and selecting the
clock automatically at runtime based on the requested mode pixel
frequency.
The input clock pins to DU channels routing is configurable, but
currently hardcoded to connect input clock i to channel i.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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The R8A7790 DU has 3 CRTCs, split in two groups. Support them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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The DU revision in the R8A7790 SoC uses one IRQ and clock per CRTC. Add
a corresponding entry in the module platform ID table.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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Channels are accessed through a global channel memory offset, there's no
need to define register addresses for the second channel.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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Several alpha plane register definitions are missing, add them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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The R-Car Display Unit (DU) DRM driver supports both superposition
processors and all eight planes in RGB and YUV formats with alpha
blending.
Only VGA and LVDS encoders and connectors are currently supported.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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