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* Merge tag 'char-misc-5.2-rc1-part2' of ↵Linus Torvalds2019-05-0724-616/+1459
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc update part 2 from Greg KH: "Here is the "real" big set of char/misc driver patches for 5.2-rc1 Loads of different driver subsystem stuff in here, all over the places: - thunderbolt driver updates - habanalabs driver updates - nvmem driver updates - extcon driver updates - intel_th driver updates - mei driver updates - coresight driver updates - soundwire driver cleanups and updates - fastrpc driver updates - other minor driver updates - chardev minor fixups Feels like this tree is getting to be a dumping ground of "small driver subsystems" these days. Which is fine with me, if it makes things easier for those subsystem maintainers. All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-5.2-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (255 commits) intel_th: msu: Add current window tracking intel_th: msu: Add a sysfs attribute to trigger window switch intel_th: msu: Correct the block wrap detection intel_th: Add switch triggering support intel_th: gth: Factor out trace start/stop intel_th: msu: Factor out pipeline draining intel_th: msu: Switch over to scatterlist intel_th: msu: Replace open-coded list_{first,last,next}_entry variants intel_th: Only report useful IRQs to subdevices intel_th: msu: Start handling IRQs intel_th: pci: Use MSI interrupt signalling intel_th: Communicate IRQ via resource intel_th: Add "rtit" source device intel_th: Skip subdevices if their MMIO is missing intel_th: Rework resource passing between glue layers and core intel_th: SPDX-ify the documentation intel_th: msu: Fix single mode with IOMMU coresight: funnel: Support static funnel dt-bindings: arm: coresight: Unify funnel DT binding coresight: replicator: Add new device id for static replicator ...
| * intel_th: msu: Add current window trackingAlexander Shishkin2019-05-031-30/+49
| | | | | | | | | | | | | | | | | | | | | | Now that we have a way to switch between MSC buffer windows, add code to track the current window. The hardware register NWSA that contains the address of the next window is unfortunately not always usable, and since the driver has full control of the window switching, there is no reason not to keep this on the software side. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: msu: Add a sysfs attribute to trigger window switchAlexander Shishkin2019-05-031-0/+28
| | | | | | | | | | | | | | | | Now that we have the means to trigger a window switch for the MSU trace store, add a sysfs file to allow triggering it from userspace. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: msu: Correct the block wrap detectionAlexander Shishkin2019-05-031-1/+1
| | | | | | | | | | | | | | | | In multi window mode the MSU will set "window wrap" bit to indicate block wrapping as well. Take this into account when checking data blocks. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: Add switch triggering supportAlexander Shishkin2019-05-034-2/+85
| | | | | | | | | | | | | | | | | | | | Add support for asserting window switch trigger when tracing to MSU output ports. This allows for software controlled switching between windows of the MSU buffer, which can be used for double buffering while exporting the trace data further from the MSU. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: gth: Factor out trace start/stopAlexander Shishkin2019-05-031-29/+64
| | | | | | | | | | | | | | | | | | | | | | | | The trace enable/disable functions of the GTH include the code that starts and stops trace flom from the sources. This start/stop functionality will also be used in the window switch trigger sequence. Factor out start/stop code from the larger trace enable/disable code in preparation for the window switch sequence. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: msu: Factor out pipeline drainingAlexander Shishkin2019-05-033-10/+29
| | | | | | | | | | | | | | | | | | | | The code that waits for the pipeline empty condition of the MSU is currently called in the path that disables the trace. We will also need this in the window switch trigger sequence. Therefore, factor out this code and make it accessible to the GTH device. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: msu: Switch over to scatterlistAlexander Shishkin2019-05-031-59/+104
| | | | | | | | | | | | | | | | | | | | | | Instead of using a home-grown array of pointers to the DMA pages, switch over to scatterlist data types and accessors, which has all the convenient accessors, can be used to batch-map DMA memory and is convenient for passing around between different layers, which will be useful when MSU buffer management has to cross the boundaries of the MSU driver. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: msu: Replace open-coded list_{first,last,next}_entry variantsAlexander Shishkin2019-05-031-10/+10
| | | | | | | | | | | | | | | | | | | | There are a few places in the code where open-coded versions of list entry accessors list_first_entry()/list_last_entry()/list_next_entry() are used. Replace those with the standard macros. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: Only report useful IRQs to subdevicesAlexander Shishkin2019-05-033-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The only type of IRQ triggering event that is useful to us at the moment is the "last block" interrupt of the MSU. This interrupt can only be enabled via "MINTCTL" register that doesn't exist in earlier version of the Intel TH. Enumerate the presence of MINTCTL via per-device driver data structure and only instantiate the IRQ resource for subdevices if this capability is present. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: msu: Start handling IRQsAlexander Shishkin2019-05-034-2/+106
| | | | | | | | | | | | | | | | | | | | | | We intend to use the interrupt to detect Last Block condition in the MSU driver, which we can use for double-buffering software-managed data transfers. Add an interrupt handler to the MSU driver. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: pci: Use MSI interrupt signallingAlexander Shishkin2019-05-032-6/+13
| | | | | | | | | | | | | | | | | | | | | | Since Intel TH is capable of MSI interrupt signalling, make use of it. The way it works is, each of the 7 interrupt triggering events has its own vector in this mode, as opposed to interrupt line delivery, where all events are signalled via the same line. Failing to enable MSI, the driver falls back to using an interrupt line. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: Communicate IRQ via resourceAlexander Shishkin2019-05-034-14/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the IRQ is passed between the glue layers and the core as a separate argument, while the MMIO resources are passed as resources. This also limits the number of IRQs thus used to one, while the current versions of Intel TH use a different MSI vector for each interrupt triggering event, of which there are 7. Change this to pass IRQ in the resources array. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: Add "rtit" source deviceAlexander Shishkin2019-05-033-3/+27
| | | | | | | | | | | | | | | | | | In some versions of Intel TH, the Software Trace Hub (STH) has a second MMIO BAR dedicated to the input from Intel PT. This calls for a new subdevice that will be enumerated if the corresponding BAR is present. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: Skip subdevices if their MMIO is missingAlexander Shishkin2019-05-031-4/+9
| | | | | | | | | | | | | | | | | | | | | | If a subdevice requires an MMIO region that wasn't in the resources passed down from the glue layer, don't instantiate it, but don't error out. This means that that particular subdevice doesn't exist for this instance of Intel TH, which is a perfectly normal situation. This applies, for example, to the "rtit" source device. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: Rework resource passing between glue layers and coreAlexander Shishkin2019-05-034-29/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, MMIO resource numbers in the TH driver core correspond to PCI BAR numbers, because in the beginning there was only the PCI glue layer. This created some confusion when the ACPI glue layer was added. To avoid confusion and remove glue-specific code from the driver core, split the resource indices between core and glue layers and change the API so that the driver core receives the MMIO resources in the same fixed order. At the same time, make the IRQ always be a parameter to intel_th_alloc() instead of sometimes passing it as a resource. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * intel_th: msu: Fix single mode with IOMMUAlexander Shishkin2019-05-031-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the pages that are allocated for the single mode of MSC are not mapped into the device's dma space and the code is incorrectly using *_to_phys() in place of a dma address. This fails with IOMMU enabled and is otherwise bad practice. Fix the single mode buffer allocation to map the pages into the device's DMA space. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Fixes: ba82664c134e ("intel_th: Add Memory Storage Unit driver") Cc: stable@vger.kernel.org # v4.4+ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: funnel: Support static funnelLeo Yan2019-05-021-27/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since CoreSight hardware topology can use a 'hidden' funnel in the trace data path, this kind funnel doesn't have register for accessing and is used by default from hardware design perspective. Below is an example for related hardware topology: +------+ +------+ | cpu0 |->| ETM |-\ +------+ +------+ \-> +--------+ +-----+ ...... | Funnel |->| ETF |-\ Hidden funnel +------+ +------+ /-> +--------+ +-----+ \ | | cpu3 |->| ETM |-/ \ V +------+ +------+ \-> +--------+ | Funnel |-> ... +------+ +------+ /-> +--------+ | cpu4 |->| ETM |-\ / +------+ +------+ \-> +--------+ +-----+ / ...... | Funnel |->| ETF |-/ +------+ +------+ /-> +--------+ +-----+ | cpu7 |->| ETM |-/ +------+ +------+ The CoreSight funnel driver only supports dynamic funnel with registration register resource, thus it cannot support for the static funnel case and it's impossible to create trace data path for this case. This patch is to extend CoreSight funnel driver to support both for static funnel and dynamic funnel. For the dynamic funnel it reuses the code existed in the driver, for static funnel the driver will support device probe if without providing register resource and the driver skips registers accessing when detect the register base is NULL. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Wanglai Shi <shiwanglai@hisilicon.com> Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: replicator: Add new device id for static replicatorLeo Yan2019-05-021-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a device id for the new static replicator compatible string; it changes the driver name from "coresight-replicator" to "coresight-static-replicator" as well. This patch also gives warning when use the replicator obsolete DT binding. Signed-off-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: etb10: Add support for CPU-wide trace scenariosMathieu Poirier2019-04-251-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc-etf: Add support for CPU-wide trace scenariosMathieu Poirier2019-04-251-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc-etr: Add support for CPU-wide trace scenariosMathieu Poirier2019-04-253-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenariosMathieu Poirier2019-04-251-3/+104
| | | | | | | | | | | | | | | | | | | | | | This patch uses the PID of the process being traced to allocate and free ETR memory buffers for CPU-wide scenarios. The implementation is tailored to handle both N:1 and 1:1 source/sink HW topologies. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc-etr: Introduce the notion of IDR to ETR devicesMathieu Poirier2019-04-252-0/+10
| | | | | | | | | | | | | | | | | | | | | | In CPU-wide scenarios with an N:1 source/sink topology, sources share the same sink. In order to reuse the same sink for all sources an IDR is needed to archive events that have already been accounted for. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc-etr: Introduce the notion of reference counting to ETR devicesMathieu Poirier2019-04-252-0/+8
| | | | | | | | | | | | | | | | | | | | This patch adds reference counting to struct etr_buf so that, in CPU-wide trace scenarios, shared buffers can be disposed of when no longer used. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc-etr: Introduce the notion of process ID to ETR devicesMathieu Poirier2019-04-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | In preparation to support CPU-wide trace scenarios, introduce the notion of process ID to ETR devices. That way events monitoring the same process can use the same etr_buf, allowing multiple CPUs to use the same sink. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc-etr: Create per-thread buffer allocation functionMathieu Poirier2019-04-251-1/+28
| | | | | | | | | | | | | | | | | | | | | | Buffer allocation is different when dealing with per-thread and CPU-wide sessions. In preparation to support CPU-wide trace scenarios simplify things by keeping allocation functions for both type separate. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf()Mathieu Poirier2019-04-251-9/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactoring function tmc_etr_setup_perf_buf() so that it only deals with the high level etr_perf_buffer, leaving the allocation of the backend buffer (i.e etr_buf) to another function. That way the backend buffer allocation function can decide if it wants to reuse an existing buffer (CPU-wide trace scenarios) or simply create a new one. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: Communicate perf event to sink buffer allocation functionsMathieu Poirier2019-04-254-15/+19
| | | | | | | | | | | | | | | | | | | | | | Make struct perf_event available to sink buffer allocation functions in order to use the pid they carry to allocate and free buffer memory along with regimenting access to what source a sink can collect data for. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: perf: Refactor function free_event_data()Mathieu Poirier2019-04-251-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | Function free_event_data() is already busy and is bound to become worse with the addition of CPU-wide trace scenarios. As such spin off a new function to strickly take care of the sink buffers. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: perf: Clean up function etm_setup_aux()Mathieu Poirier2019-04-251-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in allocating sink memory for a trace session if there is not a way to free it once it is no longer needed. As such make sure the sink API function to allocate and free memory have been implemented before moving ahead with the establishment of a trace session. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: Properly address concurrency in sink::update() functionsMathieu Poirier2019-04-252-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | When operating in CPU-wide trace scenarios and working with an N:1 source/sink HW topology, update() functions need to be made atomic in order to avoid racing with start and stop operations. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: Properly address errors in sink::disable() functionsMathieu Poirier2019-04-253-15/+12
| | | | | | | | | | | | | | | | | | | | | | | | When disabling a sink the reference counter ensures the operation goes through if nobody else is using it. As such if drvdata::mode is already set do CS_MODE_DISABLED, it is an error and should be reported as such. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: Move reference counting inside sink driversMathieu Poirier2019-04-255-29/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When operating in CPU-wide mode with an N:1 source/sink HW topology, multiple CPUs can access a sink concurrently. As such reference counting needs to happen when the device's spinlock is held to avoid racing with other operations (start(), update(), stop()), such as: session A Session B ----- ------- enable_sink atomic_inc(refcount) = 1 ... atomic_dec(refcount) = 0 enable_sink if (refcount == 0) disable_sink atomic_inc() Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: Adding return code to sink::disable() operationMathieu Poirier2019-04-255-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | In preparation to handle device reference counting inside of the sink drivers, add a return code to the sink::disable() operation so that proper action can be taken if a sink has not been disabled. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: etm4x: Configure tracers to emit timestampsMathieu Poirier2019-04-251-1/+101
| | | | | | | | | | | | | | | | | | | | Configure timestamps to be emitted at regular intervals in the trace stream to temporally correlate instructions executed on different CPUs. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: etm4x: Skip selector pair 0Mathieu Poirier2019-04-251-2/+5
| | | | | | | | | | | | | | | | | | | | | | Resource selector pair 0 is always implemented and reserved. As such it should not be explicitly programmed. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: etm4x: Add kernel configuration for CONTEXTIDMathieu Poirier2019-04-253-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Set the proper bit in the configuration register when contextID tracing has been requested by user space. That way PE_CONTEXT elements are generated by the tracers when a process is installed on a CPU. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: pmu: Adding ITRACE property to cs_etm PMUMathieu Poirier2019-04-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | Add to the capabilities the ITRACE property so that ITRACE START events are generated when the PMU is switched on by the core. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc: Cleanup power managementSuzuki K Poulose2019-04-251-2/+2
| | | | | | | | | | | | | | | | | | Drop the power only if we were successful in probing the device. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: catu: Cleanup power managementSuzuki K Poulose2019-04-251-1/+2
| | | | | | | | | | | | | | | | | | | | Drop the power handle only if we were successful. Otherwise the AMBA bus code would do the rest. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tpiu: Cleanup power managementSuzuki K Poulose2019-04-251-3/+6
| | | | | | | | | | | | | | | | | | | | | | Drop the power only when we have successfully probed. Otherwise leave it to the amba probe to do the rest. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> [Removed extra newline left after original modification] Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: etb10: Cleanup power managementSuzuki K Poulose2019-04-251-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | We drop the power before we complete the probe successfully. We are supposed to drop it only when we are successful. Also, probing the etb_buffer_length happens with the power turned up. So we don't need to do that again in the helper. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: Fix freeing up the coresight connectionsSuzuki K Poulose2019-04-251-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit c2c729415b2d2132 ("coresight: platform: Cleanup coresight connection handling"), we switched to re-using coresight_connections for the coresight_device. However, that introduced a mismatch in the alloc/free of the connections. The allocation is made using devm_*, while we use kfree() to release the memory when a device is released (even though we don't support this at the moment). Fix this by leaving it to the automatic freeing of the memory. Fixes: c2c729415b2d2132 ("coresight: platform: Cleanup coresight connection handling") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: Merge the static and dynamic replicator driversSuzuki K Poulose2019-04-254-299/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge the drivers for the two varieties of replicators into a singel one. The dynamic replicator has programming base which can be programmed to filter the trace data. The driver detects the type based on the "base" address value of the device, which is NULL for the static device. Also, while at it, remove the now obsolete DYNAMIC_REPLICATOR config entry. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: dynamic-replicator: Prepare for merging with static replicatorSuzuki K Poulose2019-04-251-41/+63
| | | | | | | | | | | | | | | | | | | | | | Rename the dynamic replicator specific routines for merging with the replicator driver. Also re-arrange the probe routine to make it easier to merge. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: replicator: Prepare for merging with dynamic-replicatorSuzuki K Poulose2019-04-251-26/+36
| | | | | | | | | | | | | | | | | | | | | | | | As a preparatory step to merge the separate drivers for static and dynamic replicators, annotate the static replicator specific details. Also refactor the probe routine to make it generic in order to merge the drivers easily. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: dynamic-replicator: Clean up error handlingSuzuki K Poulose2019-04-251-8/+16
| | | | | | | | | | | | | | | | | | | | | | We fail to disable the clock in case of a failure during the probe. Clean this up. Also, we are supposed to drop the pm reference only when the probing is successful. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: tmc: Report DMA setup failuresSuzuki K Poulose2019-04-251-1/+6
| | | | | | | | | | | | | | | | | | | | If we failed to setup the DMA mask for TMC-ETR, report the error before failing the probe. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * coresight: catu: Make catu_helper_ops and catu_ops staticYueHaibing2019-04-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix sparse warnings: drivers/hwtracing/coresight/coresight-catu.c:488:35: warning: symbol 'catu_helper_ops' was not declared. Should it be static? drivers/hwtracing/coresight/coresight-catu.c:493:28: warning: symbol 'catu_ops' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 15:23:35 +0000