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	Commit message (Collapse)	Author	Age	Files	Lines
*	irqchip/meson-gpio: Add support for Meson-AXG SoCs	Yixun Lan	2018-05-24	1	-0/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	The Meson-AXG SoC uses the same GPIO interrupt controller IP block as the other Meson SoCs. A total of 100 pins can be spied on, which is the sum of: - 255:100 Undefined(no interrupt) - 99:84, 16 pins on bank GPIOY - 83:61, 23 pins on bank GPIOX - 60:40, 21 pins on bank GPIOA - 39:25, 15 pins on bank BOOT - 24:14, 11 pins on bank GPIOZ - 13:0 , 14 pins in the AO domain Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
*	irqchip/meson-gpio: add support for Meson8 SoCs	Martin Blumenstingl	2017-11-02	1	-0/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Meson8 uses the same GPIO interrupt controller IP block as the other Meson SoCs. A total of 134 pins can be spied on, which is the sum of: - 22 pins on bank GPIOX - 17 pins on bank GPIOY - 30 pins on bank GPIODV - 10 pins on bank GPIOH - 15 pins on bank GPIOZ - 7 pins on bank CARD - 19 pins on bank BOOT - 14 pins in the AO domain Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
*	irqchip/meson: Add support for gpio interrupt controller	Jerome Brunet	2017-10-19	1	-0/+414
	Add support for the interrupt gpio controller found on Amlogic's meson SoC family. This controller is a separate controller from the gpio controller. It is able to spy on the SoC pad. It is essentially a 256 to 8 router with a filtering block to select level or edge and polarity. The number of actual mappable inputs depends on the SoC. Cc: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>