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path: root/drivers/mfd/intel_soc_pmic_bxtwc.c
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* mfd: Convert Intel PMIC drivers to use SPDX identifierAndy Shevchenko2018-10-231-9/+1
| | | | | | | | | | | 1;5201;0c Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: Sort headers alphabetically for Intel PMIC driversAndy Shevchenko2018-10-231-2/+3
| | | | | | | | | | Sort headers alphabetically for better maintenance. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Chain power button IRQs as wellAndy Shevchenko2018-10-231-10/+31
| | | | | | | | | | | | | Power button IRQ actually has a second level of interrupts to distinguish between UI and POWER buttons. Moreover, current implementation looks awkward in approach to handle second level IRQs by first level related IRQ chip. To address above issues, split power button IRQ to be chained as well. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chipsKuppuswamy Sathyanarayanan2017-06-191-30/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whishkey cove PMIC has support to mask/unmask interrupts at two levels. At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC, CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility to mask/unmask individual interrupts belong each of this domain. For example, in case of TMU, at first level we have TMU interrupt domain, and at second level we have two interrupts, wake alarm, system alarm that belong to the TMU interrupt domain. Currently, in this driver all first level IRQs are registered as part of IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ chip from your driver, all IRQs in that chip will masked and can only be enabled if that IRQ is requested using request_irq() call. This is the default Linux IRQ behavior model. And whenever a dependent device that belongs to PMIC requests only the second level IRQ and not explicitly unmask the first level IRQ, then in essence the second level IRQ will still be disabled. For example, if TMU device driver request wake_alarm IRQ and not explicitly unmask TMU level 1 IRQ then according to the default Linux IRQ model, wake_alarm IRQ will still be disabled. So the proper solution to fix this issue is to use the chained IRQ chip concept. We should chain all the second level chip IRQs to the corresponding first level IRQ. To do this, we need to create separate IRQ chips for every group of second level IRQs. In case of TMU, when adding second level IRQ chip, instead of using PMIC IRQ we should use the corresponding first level IRQ. So the following code will change from ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...) to, virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ); ret = regmap_add_irq_chip(pmic->regmap, virq, ...) In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr) to get the USBC virtual IRQ number. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Revieved-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probeKuppuswamy Sathyanarayanan2017-06-191-36/+18
| | | | | | | | | Cleanup the resource allocation/free code in probe function by using devm_* calls. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio deviceKuppuswamy Sathyanarayanan2017-06-191-6/+1
| | | | | | | | | | | | | | | | | | | | | | | Currently all PMIC GPIO domain IRQs are consumed by the same device(bxt_wcove_gpio), so there is no need to export them as separate interrupts. We can just export only the first level GPIO IRQ(BXTWC_GPIO_LVL1_IRQ) as an IRQ resource and let the GPIO device driver(bxt_wcove_gpio) handle the GPIO sub domain IRQs based on status value of GPIO level2 interrupt status register. Also, just using only the first level IRQ will eliminate the bug involved in requesting only the second level IRQ and not explicitly enable the first level IRQ. For more info on this issue please read the details at, https://lkml.org/lkml/2017/2/27/148 This patch also makes relevant change in Whiskey cove GPIO driver to use only first level PMIC GPIO IRQ. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQsKuppuswamy Sathyanarayanan2017-06-191-20/+12
| | | | | | | | | | | | | | | | | | | | | Since all second level thermal IRQs are consumed by the same device(bxt_wcove_thermal), there is no need to expose them as separate interrupts. We can just export only the first level IRQs for thermal and let the device(bxt_wcove_thermal) driver handle the second level IRQs based on thermal interrupt status register. Also, just using only the first level IRQ will eliminate the bug involved in requesting only the second level IRQ and not explicitly enable the first level IRQ. For more info on this issue please read the details at, https://lkml.org/lkml/2017/2/27/148 This patch also makes relevant change in bxt_wcove_thermal driver to use only first level PMIC thermal IRQ. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Acked-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt indexKuppuswamy Sathyanarayanan2017-06-191-1/+4
| | | | | | | | | | | | | | | | | TMU interrupts are registered as a separate interrupt chip, and hence it should start its interrupt index(BXTWC_TMU_IRQ) number from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum bxtwc_irqs_level2 and its index value is 11. Since this index value is used when calculating .num_irqs of regmap_irq_chip_tmu, it incorrectly reports number of IRQs as 12 instead of actual value of 1. This patch fixes this issue by creating new enum of tmu IRQs and resetting its starting index to 0. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: bxtwc: Remove unnecessary i2c_addr checks in ipc callsKuppuswamy Sathyanarayanan2017-04-271-12/+10
| | | | | | | | | | | | | | | | | | | In the following code block, BXTWC_DEVICE1_ADDR value is already fixed and hence there no need to check for if (!i2c_addr) in every ipc read/write calls. Even if this check is required it can be moved to probe function. i2c_addr = BXTWC_DEVICE1_ADDR; if (!i2c_addr) { dev_err(pmic->dev, "I2C address not set\n"); return -EINVAL; } This patch remove this extra check and adds some NULL parameter checks. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Rename header to follow c-fileAndy Shevchenko2017-04-271-1/+1
| | | | | | | | | | | For better understanding of relationship between headers and modules rename: intel_bxtwc.h -> intel_soc_pmic_bxtwc.h While here, remove file name from the file itself. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Move inclusion to c-fileAndy Shevchenko2017-04-271-0/+1
| | | | | | | | There is no need to include intel_soc_pmic.h into header which doesn't require it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* Merge tag 'mfd-for-linus-4.10' of ↵Linus Torvalds2016-12-191-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "New Device Support - Add support for Ricoh RC5T619 PMIC to rn5t618 - Add support for PM8821 PMIC to qcom-pm8xxx New Functionality: - Add support for GPIO to lpc_ich - Add support for GPADC to sun4i - Add ability for rk808 to shutdown Fix-ups: - Simplify/strip unnecessary code; tps65218, palmas, tps65217 - Device Tree binding updates; tps65218, altera-a10sr - Provide/export device ID info; tps65218, axp20x-i2c, hi655x-pmic, fsl-imx25-tsadc, intel_soc_pmic_bxtwc - Use MFD API instead of of_platform_populate(); tps65218 - Generalise name-space; pm8xxx - Supply/edit regmap configuration; axp20x, cs47l24-tables, axp20x - Enable compile testing; max77620, max77686, exynos-lpass, abx500-core - Coding style issues; wm8994-core, wm5102-tables - Supply endian support; syscon - Remove module support; ab3100-core, ab8500-debugfs, ab8500-gpadc, abx500-core Bug Fixes: - Fix ordering issues; wm8994 - Fix dependencies (build-time/run-time); exynos_lpass, sun4i-gpadc - Fix compiler warnings; sun4i-gpadc - Fix leaks; mfd-core - Fix page fault during module unload; tps65217" * tag 'mfd-for-linus-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (49 commits) mfd: tps65217: Support an interrupt pin as the system wakeup mfd: tps65217: Make an interrupt handler simpler mfd: tps65217: Update register interrupt mask bits instead of writing operation mfd: tps65217: Specify the IRQ name mfd: tps65217: Fix page fault on unloading modules mfd: palmas: Remove redundant check in palmas_power_off mfd: arizona: Disable IRQs during driver remove mfd: pm8xxx: add support to pm8821 mfd: intel-lpss: Try to enable Memory-Write-Invalidate mfd: rn5t618: Add Ricoh RC5T619 PMIC support mfd: axp20x: Add address extension registers for AXP806 regmap mfd: intel_soc_pmic_bxtwc: Fix a typo in MODULE_DEVICE_TABLE() mfd: core: Fix device reference leak in mfd_clone_cell mfd: bcm590xx: Simplify a test mfd: sun4i-gpadc: Select regmap-irq mfd: abx500-core: drop unused MODULE_ tags from non-modular code mfd: ab8500: make sysctrl explicitly non-modular mfd: ab8500-gpadc: Make it explicitly non-modular mfd: ab8500-debugfs: Make it explicitly non-modular mfd: ab8500-core: Make it explicitly non-modular ...
| * mfd: intel_soc_pmic_bxtwc: Fix a typo in MODULE_DEVICE_TABLE()Wei Yongjun2016-11-291-1/+1
| | | | | | | | | | | | | | | | Fix a typo in MODULE_DEVICE_TABLE(). 'pmic_acpi_ids' should be 'bxtwc_acpi_ids'. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* | Merge tag 'platform-drivers-x86-v4.10-2' of ↵Linus Torvalds2016-12-181-0/+38
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.infradead.org/users/dvhart/linux-platform-drivers-x86 Pull more x86 platform driver updates from Darren Hart: "Move and add registration for the mlx-platform driver. Introduce button and lid drivers for the surface3 (different from the surface3-pro). Add BXT PMIC TMU support. Add Y700 to existing ideapad-laptop quirk. Summary: ideapad-laptop: - Add Y700 15-ACZ to no_hw_rfkill DMI list surface3_button: - Introduce button support for the Surface 3 surface3-wmi: - Add custom surface3 platform device for controlling LID - Balance locking on error path mlx-platform: - Add mlxcpld-hotplug driver registration - Fix semicolon.cocci warnings - Move module from arch/x86 platform/x86: - Add Whiskey Cove PMIC TMU support" * tag 'platform-drivers-x86-v4.10-2' of git://git.infradead.org/users/dvhart/linux-platform-drivers-x86: platform/x86: surface3-wmi: Balance locking on error path platform/x86: Add Whiskey Cove PMIC TMU support platform/x86: ideapad-laptop: Add Y700 15-ACZ to no_hw_rfkill DMI list platform/x86: Introduce button support for the Surface 3 platform/x86: Add custom surface3 platform device for controlling LID platform/x86: mlx-platform: Add mlxcpld-hotplug driver registration platform/x86: mlx-platform: Fix semicolon.cocci warnings platform/x86: mlx-platform: Move module from arch/x86
| * | platform/x86: Add Whiskey Cove PMIC TMU supportNilesh Bacchewar2016-12-181-0/+38
| |/ | | | | | | | | | | | | | | | | | | | | This adds TMU (Time Management Unit) support for Intel BXT platform. It enables the alarm wake-up functionality in the TMU unit of Whiskey Cove PMIC. Signed-off-by: Nilesh Bacchewar <nilesh.bacchewar@intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> [andy: resolve merge conflict in Kconfig] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* / mfd: intel_soc_pmic_bxtwc: Fix usbc interruptHeikki Krogerus2016-11-161-2/+4
|/ | | | | | | | | | | | | The wcove USB Type-C driver is currently being flooded with interrupts that are not targeted to it. The reason for that is because all CHRG first level interrupts are mapped to it. This fixes the issue by introducing separate irq for the usbc device, and mapping only USB Type-C PHY interrupts to it. Fixes: 9c6235c86332 ("mfd: intel_soc_pmic_bxtwc: Add bxt_wcove_usbc device") Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: Add bxt_wcove_usbc deviceBin Gao2016-10-041-1/+22
| | | | | | | | | | The Intel Whiskey Cove PMIC includes several function units, e.g. ADC, thermal, USB Type-C, GPIO, etc. The corresponding device has to be created in the mfd driver(intel_soc_pmic_bxtwc.c). This change adds the USB Type-c device. Signed-off-by: Bin Gao <bin.gao@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: intel_soc_pmic_bxtwc: 64 bit bug in bxtwc_val_store()Dan Carpenter2015-10-301-4/+3
| | | | | | | | | | | | The call to kstrtoul() will corrupt memory on 64 bit systems because an int is 4 bytes and a long is 8. Also it's not a good idea to let users trigger a dev_err() because it just ends up flooding /var/log/messages so I removed the printk. Fixes: 2ddd2086ea9c ('mfd: add Intel Broxton Whiskey Cove PMIC driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* mfd: add Intel Broxton Whiskey Cove PMIC driverQipeng Zha2015-10-301-0/+478
Add MFD core driver for Intel Broxton Whiskey Cove PMIC, which is specially accessed by hardware IPC, not a generic I2C device Signed-off-by: Qipeng Zha <qipeng.zha@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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