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* mmc: renesas_sdhi: Add r8a7743/5 supportBiju Das2017-09-011-0/+2
| | | | | | | | | Add support for r8a7743/5 SoC.Renesas RZ/G1[ME] (R8A7743/5) SDHI is identical to the R-Car Gen2 family. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: meson-gx: fix __ffsdi2 undefined on arm32Jerome Brunet2017-08-311-7/+7
| | | | | | | | | | | | | | Using __bf_shf does not compile on arm 32 architecture. This has gone unnoticed till now cause the driver is only used on arm64. In addition, __bf_shf was already used in the driver without any issue. It was used on a constant value, so the call was probably optimized away. Replace __bf_shf by __ffs fixes the problem Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-xenon: add runtime pm support and reimplement standbyZhoujie Wu2017-08-302-16/+72
| | | | | | | | | | | | Enable runtime pm support for xenon controller, which uses 50ms auto runtime suspend by default. Reimplement system standby based on runtime pm API. Introduce restore_needed to restore the Xenon specific registers when resume. Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* Merge branch 'fixes' into nextUlf Hansson2017-08-302-3/+22
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| * mmc: sdhci-xenon: add set_power callbackZhoujie Wu2017-08-301-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xenon sdh controller requests proper SD bus voltage select bits programmed even with vmmc power supply. Any reserved value(100b-000b) programmed in this field will lead to controller ignore SD bus power bit and keep its value at zero. Add set_power callback to handle this. Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Fixes: 3a3748dba881 ("mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality") Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: block: Fix block status codesAdrian Hunter2017-08-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Commit 2a842acab109 ("block: introduce new block status code type") changed the error type but not in patches merged through the mmc tree, like commit 0493f6fe5bde ("mmc: block: Move boot partition locking into a driver op"). Fix one error code that is incorrect and also use BLK_STS_OK in preference to 0. Fixes: 17ece345a042 ("Merge tag 'mmc-v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc") Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: core: Move mmc_start_areq() declarationAdrian Hunter2017-08-301-0/+6
| | | | | | | | | | | | | | | | mmc_start_areq() is an internal mmc core API. Move the declaration accordingly. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: mmci: stop building qcom dml as moduleSrinivas Kandagatla2017-08-302-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | It does not make sense for qcom dml code to be a seperate module, as this has just 2 helper functions specific to qcom, and used directly by mmci driver, so just compile this along with main mmci driver. This would also fix issues arrising due to Kconfig combinations between mmci and qcom dml. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sunxi: Reset the device at probe timeMaxime Ripard2017-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We might be into some troubles if the bootloader misconfigured the MMC controller. We currently only de-assert the reset line at probe time, which means that if the device was already out of reset, we're going to keep whatever state was set already. Switch to a reset instead of the deassert to have a device in a pristine state when we start operating. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: rework tuning functionJerome Brunet2017-08-301-50/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | Rework tuning function of the rx phase. Now that the phase can be more precisely set using CCF, test more phase setting and find the largest working window. Then the tuning selected is the one at the center of the window. This rework allows to use new modes, such as UHS SDR50 Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: change default tx phaseJerome Brunet2017-08-301-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Initial default tx phase was set to 0 while the datasheet recommends 270. Some cards fails to initialize with this setting and eMMC mode DDR52 does not work. Changing this setting to 270 fixes these issues, without any regression so far Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: implement voltage switch callbackJerome Brunet2017-08-301-0/+22
| | | | | | | | | | | | | | | | | | | | Implement voltage switch callback (shamelessly copied from sunxi mmc driver). This allow, with the appropriate tuning function, to use SD ultra high speed modes. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: use CCF to handle the clock phasesJerome Brunet2017-08-301-41/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Several phases can be controlled on the meson-gx controller, the core, tx and rx clock phase. The tx and rx uses delays to allow more fine grained setting of the phase. To properly compute the phase using delays, accessing the clock rate is necessary. Instead of ad-hoc functions, use the common clock framework to set the clock phases (and access the clock rate while doing it). Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: implement card_busy callbackJerome Brunet2017-08-301-0/+13
| | | | | | | | | | | | | | | | | | | | Implement the card_busy callback to be able to verify that the card is done dealing with voltage switch, when the support is added later on. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: simplify interrupt handlerJerome Brunet2017-08-301-54/+39
| | | | | | | | | | | | | | | | No functional change, just improve interrupt handler readability Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: work around clk-stop issueJerome Brunet2017-08-301-6/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that the mmc clock is also used and required, somehow, by the controller itself. It is shown during init, when writing to CFG while the divider is set to 0 will crash the SoC. During a voltage switch, the controller may crash and the card may then fail to exit busy state if the clock is stopped. To avoid this, it is best to keep the clock running for the controller, except during rate change. However, we still need to be able to gate the clock out of the SoC. Let's use the pinmux for this, and fallback to gpio mode (pulled-down) when we need to gate the clock Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: fix dual data rate mode frequenciesJerome Brunet2017-08-301-12/+29
| | | | | | | | | | | | | | | | | | | | In DDR modes, meson mmc controller requires an input rate twice as fast as the output rate Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: rework clock init functionJerome Brunet2017-08-301-48/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | Thanks to devm, carrying the clock structure around after init is not necessary. Rework the function to remove these from the controller host data. Finally, set initial mmc clock rate before enabling it, simplifying the exit condition. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: rework clk_set functionJerome Brunet2017-08-301-21/+9
| | | | | | | | | | | | | | | | Clean-up clk_set function to prepare the next changes (DDR and clk-stop) Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: rework set_ios functionJerome Brunet2017-08-301-13/+9
| | | | | | | | | | | | | | | | | | Remove conditional write of cfg register. Warn if set_clk fails for some reason. Consistently use host->dev instead of mixing with mmc_dev(mmc) Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: cfg init overwrite valuesJerome Brunet2017-08-301-10/+4
| | | | | | | | | | | | | | | | | | | | | | cfg init function overwrite values set in the clk init function Remove the cfg pokes from the clk init. Actually, trying to use the CLK_AUTO, like initially tried in clk_init, would break the card initialization Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: initialize sane clk default before clock registerJerome Brunet2017-08-301-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On boot, the clock divider value is 0 which is a weird unsupported value. For example, accessing the cfg register with this value set would crash the SoC. Previous change removed 0 as possible value for CCF but forgot to properly initialize the register before registering the clock. This leads to the CCF finding an illegal value, which it complains about. Initialize the register properly in a standalone patch so the fix can be picked up if necessary. The change this fixed is: "mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag". Reported-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: mmci: constify amba_idArvind Yadav2017-08-301-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: block: cast a informative log for no devidx availableShawn Lin2017-08-301-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intention for this patch is to help folks debug the failure like this: dwmmc_rockchip fe320000.dwmmc: IDMAC supports 32-bit address mode. dwmmc_rockchip fe320000.dwmmc: Using internal DMA controller. dwmmc_rockchip fe320000.dwmmc: Version ID is 270a dwmmc_rockchip fe320000.dwmmc: DW MMC controller at irq 28,32 bit host data width,256 deep fifo dwmmc_rockchip fe320000.dwmmc: Got CD GPIO mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) mmc0: new high speed SDHC card at address 0007 mmcblk: probe of mmc0:0007 failed with error -28 The reason may be some buggy userspace daemon miss the disk remove uevent sometimes so it would finally make the SD card not work. So from the dmesg it only shows a errno of -28 but still don't understand what happened. For quick reproduce this, we could set max_devices to 8 and run for i in $(seq 1 9); do echo "========================" $i echo fe320000.dwmmc > /sys/bus/platform/drivers/dwmmc_rockchip/unbind sleep .5 echo fe320000.dwmmc > /sys/bus/platform/drivers/dwmmc_rockchip/bind sleep .5 mount -t vfat /dev/mmcblk0 /mnt sleep .5 done Another possible reason would be the device has more partitions than what we support, so that they have to increase their max_devices. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-pltfm: export sdhci_pltfm_suspend/resumeMasahiro Yamada2017-08-303-21/+7
| | | | | | | | | | | | | | | | | | This will be useful when drivers want to reuse either suspend or resume callback instead of whole of sdhci_pltfm_pmops. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci: enable/disable the clock in sdhci_pltfm_suspend/resumeMasahiro Yamada2017-08-303-76/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit provides similar cleanups as commit 83eacdfa2529 ("mmc: sdhci: disable the clock in sdhci_pltfm_unregister()") did for unregister hooks. sdhci-brcmstb.c and sdhci-sirf.c implement their own suspend/resume hooks to handle pltfm_host->clk. Move clock handling to sdhci_pltfm.c so that the drivers can reuse sdhci_pltfm_pmops. The following drivers did not previously touch pltfm_host->clk during suspend/resume, but now do: - sdhci-bcm-kona.c - sdhci-dove.c - sdhci-iproc.c - sdhci-pxav2.c - sdhci-tegra.c - sdhci-xenon.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Al Cooper <alcooperx@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-pxav2: switch to managed clk and sdhci_pltfm_unregister()Masahiro Yamada2017-08-301-23/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The difference between sdhci_pxav2_remove() and sdhci_pltfm_unregister() is clk_put(). It will go away by using the managed resource clk, then sdhci_pltfm_unregister() can be reused. Also, rename the jump labels to say what the goto does. (Coding style suggested by Documentation/process/coding-style.rst) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-cadence: add suspend / resume supportMasahiro Yamada2017-08-301-9/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the probe function initializes the PHY, but PHY settings are lost during the sleep state. Restore the PHY registers when resuming. To facilitate this, split sdhci_cdns_phy_init() into the DT parse part and PHY update part so that the latter can be invoked from the resume hook. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-xenon: Support HS400 Enhanced Strobe featureHu Ziji2017-08-302-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | Support HS400 Enhanced Strobe feature in Xenon. Enable Enhanced Strobe together with Data Strobe. Disable Enhanced Strobe when eMMC is not in HS400 mode. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci: Add quirk to indicate MMC_RSP_136 has CRCKishon Vijay Abraham I2017-08-302-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | TI's implementation of sdhci controller used in DRA7 SoC's has CRC in responses with length 136 bits. Add quirk to indicate the controller has CRC in MMC_RSP_136. If this quirk is set sdhci library shouldn't shift the response present in SDHCI_RESPONSE register. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci: Tidy reading 136-bit responsesAdrian Hunter2017-08-301-10/+18
| | | | | | | | | | | | | | | | | | Read each register only once and move the code to a separate function so that it is not jammed against the 80 column margin. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: clean up some constantsJerome Brunet2017-08-301-3/+1
| | | | | | | | | | | | | | | | | | | | | | Remove unused clock rate defines. These should not be defined but requested from the clock framework. Also correct typo on the DELAY register Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flagJerome Brunet2017-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider with a 0 value will behave as a bypass clock The mmc divider does not behave like this, a 0 value disables the clock Remove this flag so CCF never allows a 0 value on this clock Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: meson-gx: fix mux mask definitionJerome Brunet2017-08-301-1/+1
| | | | | | | | | | | | | | | | | | CCF generic mux will shift the mask using the value defined in shift Define the mask accordingly Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: block: Reparametrize mmc_blk_ioctl_[multi]_cmd()Linus Walleij2017-08-301-25/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of passing a block device to mmc_blk_ioctl[_multi]_cmd(), let's pass struct mmc_blk_data() so we operate ioctl()s on the MMC block device representation rather than the vanilla block device. This saves a little duplicated code and makes it possible to issue ioctl()s not targeted for a specific block device but rather for a specific partition/area. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: block: Refactor mmc_blk_part_switch()Linus Walleij2017-08-301-12/+13
| | | | | | | | | | | | | | | | | | | | | | Instead of passing a struct mmc_blk_data * to mmc_blk_part_switch() let's pass the actual partition type we want to switch to. This is necessary in order not to have a block device with a backing mmc_blk_data and request queue and all for every hardware partition, such as RPMB. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: block: Move duplicate checkLinus Walleij2017-08-301-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | mmc_blk_ioctl() calls either mmc_blk_ioctl_cmd() or mmc_blk_ioctl_multi_cmd() and each of these make the same check. Factor it into a new helper function, call it on both branches of the switch() statement and save a chunk of duplicate code. Cc: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: debugfs: Move block debugfs into block moduleLinus Walleij2017-08-303-89/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we don't have the block layer enabled, we do not present card status and extcsd in the debugfs. Debugfs is not ABI, and maintaining files of no relevance for non-block devices comes at a high maintenance cost if we shall support it with the block layer compiled out. The debugfs entries suffer from all the same starvation issues as the other userspace things, under e.g. a heavy dd operation. The expected number of debugfs users utilizing these two debugfs files is already low as there is an ioctl() to get the same information using the mmc-tools, and of these few users the expected number of people using it on SDIO or combo cards are expected to be zero. It is therefore logical to move this over to the block layer when it is enabled, using the new custom requests and issue it using the block request queue. On the other hand it moves some debugfs code from debugfs.c and into block.c. Tested during heavy dd load by cat:in the status file. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: ops: export mmc_get_status()Linus Walleij2017-08-301-0/+1
| | | | | | | | | | | | | | | | | | | | This function retrieves the status of the card with the default number of retries. Since the block layer wants to use this, and since the block layer is a loadable kernel module, we need to export this symbol. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: block: Anonymize the drv op data pointerLinus Walleij2017-08-302-4/+6
| | | | | | | | | | | | | | | | | | We have a data pointer for the ioctl() data, but we need to pass other data along with the DRV_OP:s, so make this a void * so it can be reused. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: cavium-octeon: Convert to use module_platform_driverAxel Lin2017-08-301-12/+1
| | | | | | | | | | | | | | | | Get rid of boilerplate code by using module_platform_driver macro. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: test: reduce stack usage in mmc_test_nonblock_transferArnd Bergmann2017-08-301-56/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new lockdep annotations for completions cause a warning in the mmc test module, in a function that now has four 150 byte structures on the stack: drivers/mmc/core/mmc_test.c: In function 'mmc_test_nonblock_transfer.constprop': drivers/mmc/core/mmc_test.c:892:1: error: the frame size of 1360 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] The mmc_test_ongoing_transfer function evidently had a similar problem, and worked around it by using dynamic allocation. This generalizes the approach used by mmc_test_ongoing_transfer() and applies it to mmc_test_nonblock_transfer() as well. Fixes: cd8084f91c02 ("locking/lockdep: Apply crossrelease to completions") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-of-esdhc: support ESDHC_CAPABILITIES_1 accessingyangbo lu2017-08-302-2/+24
| | | | | | | | | | | | | | | | | | | | eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handlingyangbo lu2017-08-301-13/+14
| | | | | | | | | | | | | | | | | | | | | | SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably use high speed enable bit for other purpose. So this bit shouldn't be changed for high speed enabling for this type of SD controller. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-s3c: use generic sdhci_set_bus_width()Michał Mirosław2017-08-301-33/+1
| | | | | | | | | | | | | | | | | | | | | | Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-s3c version with the generic sdhci version. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-pci: use generic sdhci_set_bus_width()Michał Mirosław2017-08-301-27/+3
| | | | | | | | | | | | | | | | | | | | Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-pci version with the generic sdhci version. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci-tegra: use generic sdhci_set_bus_width()Michał Mirosław2017-08-301-21/+2
| | | | | | | | | | | | | | | | | | | | | | Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the tegra version with the generic sdhci version. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci: key 8BITBUS bit off MMC_CAP_8_BIT_DATAMichał Mirosław2017-08-301-3/+2
| | | | | | | | | | | | | | | | | | | | | | Hosts supporting 8-bit bus are marked accordingly. If MMC_CAP_8_BIT_DATA is not among host capabilities, 8BITBUS bit will never be set and it is not cleared in case some non-SDHCI3 host uses it for something else. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: core: Turn off CQE before sending commandsAdrian Hunter2017-08-301-0/+9
| | | | | | | | | | | | | | | | | | | | CQE needs to be off for the host controller to accept non-CQ commands. Turn off the CQE before sending commands, and ensure it is off in any reset or power management paths, or re-tuning. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: core: Add mmc_retune_hold_now()Adrian Hunter2017-08-302-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | mmc_return_hold() / mmc_retune_release() are used around a group of commands to prevent re-tuning between the commands. Re-tuning can still happen before the first command. In some cases, re-tuning must be prevented entirely. Add mmc_retune_hold_now() for that purpose. It is added in preparation for CQE support where it will be used by CQE recovery. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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