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* scripts/spelling.txt: add "disble(d)" pattern and fix typo instancesMasahiro Yamada2017-03-091-1/+1
| | | | | | | | | | | | | | | | Fix typos and add the following to the scripts/spelling.txt: disble||disable disbled||disabled I kept the TSL2563_INT_DISBLED in /drivers/iio/light/tsl2563.c untouched. The macro is not referenced at all, but this commit is touching only comment blocks just in case. Link: http://lkml.kernel.org/r/1481573103-11329-20-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mtd: aspeed: remove redundant dev_err call in aspeed_smc_probe()Wei Yongjun2017-02-101-6/+2
| | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* Merge tag 'spi-nor/for-4.11-v2' of git://github.com/spi-nor/linuxBrian Norris2017-02-109-67/+1913
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Cyrille: """ This pull request contains the following notable changes: - add support to the 4-byte address instruction set. - add support to new memory parts. - add support to S3AN memories. - add support to the Intel SPI controller. - add support to the Aspeed AST2400 and AST2550 controllers. - fix max SPI transfer and message sizes in m25p80_read(). - fix the Candence QSPI driver. - fix the Freescale QSPI driver. """
| * mtd: spi-nor: cqspi: remove redundant dead code on error return checkColin Ian King2017-02-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | Checking for ret < 0 is redundant because a previous check on ret being non-zero already handles the ret < 0 case. Remove the redundant code. Found by CoverityScan, CID#1398863, CID#1398864 Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Richard Weinberger <richard@nod.at> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READYunhui Cui2017-02-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | There are some read modes for flash, such as NORMAL, FAST, QUAD, DDR QUAD. These modes will use the identical lut table base So rename SEQID_QUAD_READ to SEQID_READ. Signed-off-by: Yunhui Cui <B56489@freescale.com> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * mtd:fsl-quadspi:use the property fields of SPI-NORYunhui Cui2017-02-101-28/+12
| | | | | | | | | | | | | | | | | | | | | | We can get the read/write/erase opcode from the spi nor framework directly. This patch uses the information stored in the SPI-NOR to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by: Yunhui Cui <B56489@freescale.com> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * mtd: spi-nor: Add support for gd25q16Kamal Dasu2017-02-101-0/+5
| | | | | | | | | | | | | | | | Add GigaDevice GD25Q16 (16M-bit) to supported list. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * mtd: spi-nor: Fix S3AN addressing calculationRicardo Ribalda2017-02-101-3/+6
| | | | | | | | | | | | | | | | | | The page calculation under spi_nor_s3an_addr_convert() was wrong. On Default Address Mode we need to perform a divide by page_size. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * mtd: aspeed: fix compile warning in aspeed_smc_read_from_ahb()Cédric Le Goater2017-02-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The first argument of ioread32_rep() and ioread8_rep is not const. Change aspeed_smc_read_from_ahb() prototype to fix compile warning : drivers/mtd/spi-nor/aspeed-smc.c: In function 'aspeed_smc_read_from_ahb': drivers/mtd/spi-nor/aspeed-smc.c:212:16: warning: passing argument 1 of 'ioread32_rep' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] ioread32_rep(src, buf, len >> 2); Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * Merge tag 'ib-mfd-mtd-v4.11' of ↵Cyrille Pitchen2017-02-105-0/+880
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd From Lee Jones: """ Immutable branch between MFD and MTD due for the v4.11 merge window """
| | * spi-nor: Add support for Intel SPI serial flash controllerMika Westerberg2017-01-035-0/+880
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the SPI serial flash host controller found on many Intel CPUs including Baytrail and Braswell. The SPI serial flash controller is used to access BIOS and other platform specific information. By default the driver exposes a single read-only MTD device but with a module parameter "writeable=1" the MTD device can be made read-write which makes it possible to upgrade BIOS directly from Linux. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
| * | mtd: spi-nor: Add lock/unlock support for f25l32paVictor Shyba2017-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This chip has write protection enabled on power-up, so this flag is necessary to support write operations. Signed-off-by: Victor Shyba <victor1984@riseup.net> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * | mtd: spi-nor: add a stateless method to support memory size above 128MibCyrille Pitchen2017-02-101-21/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides an alternative mean to support memory above 16MiB (128Mib) by replacing 3byte address op codes by their associated 4byte address versions. Using the dedicated 4byte address op codes doesn't change the internal state of the SPI NOR memory as opposed to using other means such as updating a Base Address Register (BAR) and sending command to enter/leave the 4byte mode. Hence when a CPU reset occurs, early bootloaders don't need to be aware of BAR value or 4byte mode being enabled: they can still access the first 16MiB of the SPI NOR memory using the regular 3byte address op codes. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Tested-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
| * | mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address op codesCyrille Pitchen2017-02-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames the SPINOR_OP_* macros of the 4-byte address instruction set so the new names all share a common pattern: the 4-byte address name is built from the 3-byte address name appending the "_4B" suffix. The patch also introduces new op codes to support other SPI protocols such as SPI 1-4-4 and SPI 1-2-2. This is a transitional patch and will help a later patch of spi-nor.c to automate the translation from the 3-byte address op codes into their 4-byte address version. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Marek Vasut <marek.vasut@gmail.com>
| * | mtd: aspeed: add memory controllers for the Aspeed AST2400 SoCCédric Le Goater2017-02-102-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds mtd support for the Aspeed AST2400 SoC static memory controllers: * New Static Memory Controller (referred as FMC) . BMC firmware . AST2500 compatible register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. * SPI Flash Controller (SPI) . host Firmware . slightly different register set, between AST2500 and the legacy controller . supports SPI flash memory . 1 chip select pin (CE0) The legacy static memory controller (referred as SMC) is not supported, as well as types other than SPI. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * | mtd: spi-nor: add memory controllers for the Aspeed AST2500 SoCCédric Le Goater2017-02-103-0/+737
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds mtd support for the Aspeed AST2500 SoC static memory controllers : * Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver * SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . supports SPI type flash memory Each controller has a memory range on which it maps its flash module slaves. Each slave is assigned a memory window for its mapping that can be changed at bootime with the Segment Address Register. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Currently, only the User mode is supported. Command mode needs a little more work to check that the memory window on the AHB bus fits the module size. Based on previous work from Milton D. Miller II <miltonm@us.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * | mtd: spi-nor: remove WARN_ONCE() message in spi_nor_write()Cyrille Pitchen2017-02-101-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the WARN_ONCE() test in spi_nor_write(). This macro triggers the display of a warning message almost every time we use a UBI file-system because a write operation is performed at offset 64, which is in the middle of the SPI NOR memory page. This is a valid operation for ubifs. Hence this warning is pretty annoying and useless so we just remove it. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Suggested-by: Richard Weinberger <richard@nod.at> Suggested-by: Andras Szemzo <szemzo.andras@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | mtd: spi-nor: improve macronix_quad_enable()Cyrille Pitchen2017-02-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch checks whether the Quad Enable bit is already set in the Status Register. If so, the function exits immediately with a successful return code. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
| * | mtd: spi-nor: Add support for S3AN spi-nor devicesRicardo Ribalda2017-02-101-5/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep their configuration data and (optionally) some user data. The protocol of this flash follows most of the spi-nor standard. With the following differences: - Page size might not be a power of two. - The address calculation (default addressing mode). - The spi nor commands used. Protocol is described on Xilinx User Guide UG333 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
| * | mtd: spi-nor: cqspi: Fix build on arches missing readsl/writeslMarek Vasut2017-01-042-3/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The x86-64 and some other architectures are missing readsl/writesl functions, so this driver won't build on them. Use a more portable ioread32_rep()/iowrite32_rep() instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Suggested-by: Stefan Roese <sr@denx.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* / mtd: Fix typo: "occured" -> "occurred"Nobuhiro Iwamatsu2017-02-081-2/+2
|/ | | | | | | Trivial typo fix in comment. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: constify fsl_qspi_devtype_dataLABBE Corentin2016-11-261-4/+4
| | | | | | | | | All fsl_qspi_devtype_data structures are never modified. This patch constify them. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: Add support for mr25h40IWAMOTO Masahiko2016-11-261-0/+1
| | | | | | | | | Add Everspin mr25h40 512KB MRAM to the list of supported chips. Signed-off-by: Masahiko Iwamoto <iwamoto@allied-telesis.co.jp> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: Add support for N25Q016AMoritz Fischer2016-11-261-0/+1
| | | | | | | | | | | | | This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Jagan Teki <jteki@openedev.com> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: Add at25df321 spi-nor flash supportJagan Teki2016-11-261-0/+1
| | | | | | | | | | Add Atmel at25df321 spi-nor flash to the list of spi_nor_ids. Cc: Brian Norris <computersforpeace@gmail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: Fix some error codes in cqspi_setup_flash()Dan Carpenter2016-11-261-1/+3
| | | | | | | | | | | We return success or possibly uninitialized values on these error paths instead of proper error codes. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: Off by one in cqspi_setup_flash()Dan Carpenter2016-11-261-1/+1
| | | | | | | | | | There are CQSPI_MAX_CHIPSELECT elements in the ->f_pdata array so the > should be >=. Fixes: 140623410536 ('mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: add support for s25fl208kSean Nyekjaer2016-11-261-0/+1
| | | | | | | Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: fix flags for s25fl128sHeiner Kallweit2016-11-261-1/+1
| | | | | | | | | | | The Spansion S25FL128S also supports dual read mode. In addition remove flag SECT_4K. 4K erases are supported, but not uniformly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: fix spansion quad enableJoël Esponde2016-11-231-0/+7
| | | | | | | | | | | | | | | | | With the S25FL127S nor flash part, each writing to the configuration register takes hundreds of ms. During that time, no more accesses to the flash should be done (even reads). This commit adds a wait loop after the register writing until the flash finishes its work. This issue could make rootfs mounting fail when the latter was done too much closely to this quad enable bit setting step. And in this case, a driver as UBIFS may try to recover the filesystem and may broke it completely. Signed-off-by: Joël Esponde <joel.esponde@honeywell.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: add Macronix mx25u25635f to list of known devices.Ash Benz2016-11-231-0/+1
| | | | | Signed-off-by: Ash Benz <ash.benz@bk.ru> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
* mtd: spi-nor: don't build Cadence QuadSPI on non-ARMBrian Norris2016-07-191-1/+1
| | | | | | | | | | This controller driver is used only on ARM but is mostly written portably so it can build on other arch'es. Unfortunately, at least x86 doesn't provibe readsl()/writesl() accessors. We could possibly fix this issue in the future by using io{read,write}32_rep() instead, but let's just drop the architectures we aren't using for now. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: mtk-nor: remove duplicated include from mtk-quadspi.cWei Yongjun2016-07-191-1/+0
| | | | | | | Remove duplicated include. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: Add driver for Cadence Quad SPI Flash ControllerGraham Moore2016-07-183-0/+1311
| | | | | | | | | | | | | | | | | | Add support for the Cadence QSPI controller. This controller is present in the Altera SoCFPGA SoCs and this driver has been tested on the Cyclone V SoC. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@opensource.altera.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Graham Moore <grmoore@opensource.altera.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Yves Vandervennet <yvanderv@opensource.altera.com> Cc: devicetree@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: atmel-quadspi: add driver for Atmel QSPI controllerCyrille Pitchen2016-07-153-0/+742
| | | | | | | | | | This driver add support to the new Atmel QSPI controller embedded into sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI controller. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: add hisilicon spi-nor flash controller driverJiancheng Xue2016-07-133-0/+497
| | | | | | | | | | | | Add hisilicon spi-nor flash controller driver Signed-off-by: Binquan Peng <pengbinquan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: support dual, quad, and WP for GigadeviceBrian Norris2016-07-131-4/+20
| | | | | | | | | | | | | | | | Gigadevice flash support BP{0,1,2,3,4} bits, where BP3 means the same as the existing supported TB (Top/Bottom), and BP4 means the same as the not-yet-supported 4K bit used on other flash (e.g., Winbond). Let's support lock/unlock with the same feature flags as w25q32dw/w25q64dw. Tested on gd25lq64c, but I checked datasheets for the other 3, to make sure. While I was at it, I noticed that these all support dual and quad as well. I noted them, but can't test them at the moment, since my test system only supports standard 1x SPI. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: Added support for n25q00a.P L Sai Krishna2016-07-131-0/+1
| | | | | | | | | | | Add Micron (n25q00a) 1Gbit NOR Flash in the list of supported devices. This part is different from n25q00 in Memory Type. Memory Type for n25q00 - BAh Memory Type for n25q00a - BBh Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: fix wrong "fully unlocked" testBrian Norris2016-07-091-1/+1
| | | | | | | | | | | | | | | | | In stm_unlock(), the test to determine whether we've fully unlocked the flash checks for the lock length to be equal to the flash size. That is a typo/think-o -- the condition actually means the flash is completely *locked.* We should be using the inverse condition -- that the lock length is 0 (i.e., no protection). The result of this bug is that we never actually turn off the Status Register Write Disable bit, even if the flash is completely unlocked. Now we can. Fixes: 47b8edbf0d43 ("mtd: spi-nor: disallow further writes to SR if WP# is low") Reported-by: Giorgio <giorgio.nicole@arcor.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* mtd: spi-nor: add read loopMichal Suchanek2016-06-011-6/+19
| | | | | | | | | | | | mtdblock and ubi do not handle the situation when read returns less data than requested. Loop in spi-nor until buffer is filled or an error is returned. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
* mtd: spi-nor: simplify write loopMichal Suchanek2016-06-011-33/+25
| | | | | | | | | | | | | | | The spi-nor write loop assumes that what is passed to the hardware driver write() is what gets written. When write() writes less than page size at once data is dropped on the floor. Check the amount of data writen and exit if it does not match requested amount. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
* mtd: spi-nor: stop passing around retlenMichal Suchanek2016-06-014-28/+24
| | | | | | | | | | | Do not pass retlen to hardware driver read/write functions. Update it in spi-nor generic driver instead. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
* mtd: spi-nor: check return value from writeMichal Suchanek2016-06-011-13/+32
| | | | | | | | | | | SPI NOR hardware drivers now return useful value from their write functions so check them. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
* mtd: nxp-spifi: return amount of data transferred or error in read/writeBrian Norris2016-06-011-4/+9
| | | | | | | Add checking of SPI transfer errors and return them from read/write functions. Also return the amount of data transferred. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: mtk-quadspi: return amount of data transferred or error in read/writeBrian Norris2016-06-011-7/+7
| | | | | | | Add checking of SPI transfer errors and return them from read/write functions. Also return the amount of data transferred. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: fsl-quadspi: return amount of data read/written or errorMichal Suchanek2016-06-011-6/+11
| | | | | | | Return amount of data read/written or error as read(2)/write(2) does. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: change return value of read/writeMichal Suchanek2016-06-014-17/+31
| | | | | | | | | | | | | | | | | | Change the return value of spi-nor device read and write methods to allow returning amount of data transferred and errors as read(2)/write(2) does. Also, start handling positive returns in spi_nor_read(), since we want to convert drivers to start returning the read-length both via *retlen and the return code. (We don't need to do the same transition process for spi_nor_write(), since ->write() didn't used to have a return code at all.) Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Michal Suchanek <hramrach@gmail.com> Tested-by: Michal Suchanek <hramrach@gmail.com>
* mtd: spi-nor: support GigaDevice gd25lq64cBrian Norris2016-05-101-0/+1
| | | | | | | | | | | Also note the GigaDevice JEDEC ID. No write-protect support yet, since this flash uses a different status register layout. Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* mtd: spi-nor: support lock/unlock for a few Winbond chipsBrian Norris2016-03-071-3/+15
| | | | | | | | | | | | | | | | These are recent Winbond models that are known to have lock/unlock support via writing the Status Register, and that also support the TB (Top/Bottom) protection bit. Tested on w25q32dw. [Note on style: these entries are getting pretty long lines, so I picked a style that seems reasonable for splitting up the flags separate from the other mostly-similar fields.] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* mtd: spi-nor: add TB (Top/Bottom) protect supportBrian Norris2016-03-071-7/+63
| | | | | | | | | | | | Some flash support a bit in the status register that inverts protection so that it applies to the bottom of the flash, not the top. This yields additions to the protection range table, as noted in the comments. Because this feature is not universal to all flash that support lock/unlock, control it via a new flag. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
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