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path: root/drivers/net/ethernet/amd/xgbe/xgbe.h
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* amd-xgbe: use enums for mailbox cmd and sub_cmdsRaju Rangoju2022-10-211-0/+25
| | | | | | | | | Instead of using hardcoded values, use enumerations for mailbox command and sub commands. Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* amd-xgbe: Yellow carp devices do not need rrcRaju Rangoju2022-10-211-0/+1
| | | | | | | | | | | | | Link stability issues are noticed on Yellow carp platforms when Receiver Reset Cycle is issued. Since the CDR workaround is disabled on these platforms, the Receiver Reset Cycle is not needed. So, avoid issuing rrc on Yellow carp platforms. Fixes: dbb6c58b5a61 ("net: amd-xgbe: Add Support for Yellow Carp Ethernet device") Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* amd/xgbe: fix repeated words in commentsJilin Yuan2022-06-271-1/+1
| | | | | | | | Delete the redundant word 'use'. Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com> Link: https://lore.kernel.org/r/20220625070633.64982-1-yuanjilin@cdjrlc.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* net: allow gso_max_size to exceed 65536Alexander Duyck2022-05-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The code for gso_max_size was added originally to allow for debugging and workaround of buggy devices that couldn't support TSO with blocks 64K in size. The original reason for limiting it to 64K was because that was the existing limits of IPv4 and non-jumbogram IPv6 length fields. With the addition of Big TCP we can remove this limit and allow the value to potentially go up to UINT_MAX and instead be limited by the tso_max_size value. So in order to support this we need to go through and clean up the remaining users of the gso_max_size value so that the values will cap at 64K for non-TCPv6 flows. In addition we can clean up the GSO_MAX_SIZE value so that 64K becomes GSO_LEGACY_MAX_SIZE and UINT_MAX will now be the upper limit for GSO_MAX_SIZE. v6: (edumazet) fixed a compile error if CONFIG_IPV6=n, in a new sk_trim_gso_size() helper. netif_set_tso_max_size() caps the requested TSO size with GSO_MAX_SIZE. Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Signed-off-by: Eric Dumazet <edumazet@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ethernet: constify references to netdev->dev_addr in driversJakub Kicinski2021-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | This big patch sprinkles const on local variables and function arguments which may refer to netdev->dev_addr. Commit 406f42fa0d3c ("net-next: When a bond have a massive amount of VLANs...") introduced a rbtree for faster Ethernet address look up. To maintain netdev->dev_addr in this tree we need to make all the writes to it got through appropriate helpers. Some of the changes here are not strictly required - const is sometimes cast off but pointer is not used for writing. It seems like it's still better to add the const in case the code changes later or relevant -W flags get enabled for the build. No functional changes. Link: https://lore.kernel.org/r/20211014142432.449314-1-kuba@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* amd-xgbe: Update DMA coherency valuesShyam Sundar S K2021-03-251-3/+3
| | | | | | | | | | | Based on the IOMMU configuration, the current cache control settings can result in possible coherency issues. The hardware team has recommended new settings for the PCI device path to eliminate the issue. Fixes: 6f595959c095 ("amd-xgbe: Adjust register settings to improve performance") Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* xgbe: convert to new udp_tunnel_nic infraJakub Kicinski2020-07-141-12/+1
| | | | | | | | | | | | | | | | | | | | | Make use of the new udp_tunnel_nic infra. Don't clear the features when VxLAN port is not present to make all drivers behave the same. Driver will now (until we address the problem in the core) leave the RX UDP tunnel feature always on, since this is what most drivers do. Remove the list of VxLAN ports, just program the one core told us to. The driver seem to want to clear the VxLAN ports on close but it doesn't seem to flush the port list properly so it'd get wrong use counts after close/open. Again since it calls its own open handler we need the reset notification hack. v2: - fix kbuild warning Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* net/amd: Remove useless driver versionLeon Romanovsky2020-02-241-1/+0
| | | | | | | Convert AMD drivers to respect universal linux kernel version. Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Improve SFP 100Mbps auto-negotiationTom Lendacky2018-05-231-0/+1
| | | | | | | | | | | | | After changing speed to 100Mbps as a result of auto-negotiation (AN), some 10/100/1000Mbps SFPs indicate a successful link (no faults or loss of signal), but cannot successfully transmit or receive data. These SFPs required an extra auto-negotiation (AN) after the speed change in order to operate properly. Add a quirk for these SFPs so that if the outcome of the AN actually results in changing to a new speed, re-initiate AN at that new speed. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add ethtool show/set channels supportTom Lendacky2018-05-231-0/+4
| | | | | | | | Add ethtool support to show and set the device channel configuration. Changing the channel configuration will result in a device restart. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add ethtool show/set ring parameter supportTom Lendacky2018-05-231-0/+6
| | | | | | | | | Add ethtool support to show and set the number of the Rx and Tx ring descriptors. Changing the ring configuration will result in a device restart. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add ethtool support to retrieve SFP module infoTom Lendacky2018-05-231-0/+13
| | | | | | | Add support to get SFP module information using ethtool. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Read and save the port property registers during probeTom Lendacky2018-05-231-0/+7
| | | | | | | | Read and save the port property registers once during the device probe and then use the saved values as they are needed. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Improve KR auto-negotiation and trainingTom Lendacky2018-04-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Update xgbe-phy-v2.c to make use of the auto-negotiation (AN) phy hooks to improve the ability to successfully complete Clause 73 AN when running at 10gbps. Hardware can sometimes have issues with CDR lock when the AN DME page exchange is being performed. The AN and KR training hooks are used as follows: - The pre AN hook is used to disable CDR tracking in the PHY so that the DME page exchange can be successfully and consistently completed. - The post KR training hook is used to re-enable the CDR tracking so that KR training can successfully complete. - The post AN hook is used to check for an unsuccessful AN which will increase a CDR tracking enablement delay (up to a maximum value). Add two debugfs entries to allow control over use of the CDR tracking workaround. The debugfs entries allow the CDR tracking workaround to be disabled and determine whether to re-enable CDR tracking before or after link training has been initiated. Also, with these changes the receiver reset cycle that is performed during the link status check can be performed less often. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add pre/post auto-negotiation phy hooksTom Lendacky2018-04-231-0/+5
| | | | | | | | Add hooks to the driver auto-negotiation (AN) flow to allow the different phy implementations to perform any steps necessary to improve AN. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add additional ethtool statisticsLendacky, Thomas2017-08-181-0/+5
| | | | | | | | Add some additional statistics for tracking VXLAN packets and checksum errors. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for VXLAN offload capabilitiesLendacky, Thomas2017-08-181-0/+22
| | | | | | | | | | | | | The hardware has the capability to perform checksum offload support (both Tx and Rx) and TSO support for VXLAN packets. Add the support required to enable this. The hardware can only support a single VXLAN port for offload. If more than one VXLAN port is added then the offload capabilities have to be disabled and can no longer be advertised. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Convert to using the new link mode settingsLendacky, Thomas2017-08-181-4/+46
| | | | | | | | | Convert from using the old u32 supported, advertising, etc. link settings to the new link mode settings that support bit positions / settings greater than 32 bits. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add per queue Tx and Rx statisticsLendacky, Thomas2017-08-181-0/+5
| | | | | | | Add per queue Tx and Rx packet and byte counts. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Optimize DMA channel interrupt enablementLendacky, Thomas2017-08-181-2/+2
| | | | | | | | | | | | | | | Currently whenever the driver needs to enable or disable interrupts for a DMA channel it reads the interrupt enable register (IER), updates the value and then writes the new value back to the IER. Since the hardware does not change the IER, software can track this value and elimiate the need to read it each time. Add the IER value to the channel related data structure and use that as the base for enabling and disabling interrupts, thus removing the need for the MMIO read. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support to handle device renamingLendacky, Thomas2017-08-181-2/+3
| | | | | | | | | | | | | | Many of the names used by the driver are based upon the name of the device found during device probe. Move the formatting of the names into the device open function so that any renaming that occurs before the device is brought up will be accounted for. This also means moving the creation of some named workqueues into the device open path. Add support to register for net events so that if a device is renamed the corresponding debugfs directory can be renamed. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* drivers: net: add missing interrupt.h includeFlorian Westphal2017-07-181-0/+1
| | | | | | | | | these drivers use tasklets or irq apis, but don't include interrupt.h. Once flow cache is removed the implicit interrupt.h inclusion goes away which will break the build. Signed-off-by: Florian Westphal <fw@strlen.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Adjust register settings to improve performanceLendacky, Thomas2017-06-291-0/+11
| | | | | | | | | | | | | | | | | Add support to change some general performance settings and to provide some performance settings based on the device that is probed. This includes: - Setting the maximum read/write outstanding request limit - Reducing the AXI interface burst length size - Selectively setting the Tx and Rx descriptor pre-fetch threshold - Selectively setting additional cache coherency controls Tested and verified on all versions of the hardware. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Simplify the burst length settingsLendacky, Thomas2017-06-291-10/+2
| | | | | | | | | | | | | | Currently the driver hardcodes the PBLx8 setting. Remove the need for specifying the PBLx8 setting and automatically calculate based on the specified PBL value. Since the PBLx8 setting applies to both Tx and Rx use the same PBL value for both of them. Also, the driver currently uses a bit field to set the AXI master burst len setting. Change to the full bit field range and set the burst length based on the specified value. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for more fine grained cache coherency controlsLendacky, Thomas2017-06-291-9/+6
| | | | | | | | | In prep for setting fine grained read and write DMA cache coherency controls, allow specific values to be used to set the cache coherency registers. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add NUMA affinity support for IRQ hintsLendacky, Thomas2017-06-291-0/+2
| | | | | | | | For IRQ affinity, set the affinity hints for the IRQs to be (initially) on the processors corresponding to the NUMA node of the device. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add NUMA affinity support for memory allocationsLendacky, Thomas2017-06-291-1/+4
| | | | | | | | | | | Add support to perform memory allocations on the node of the device. The original allocation or the ring structure and Tx/Rx queues allocated all of the memory at once and then carved it up for each channel and queue. To best ensure that we get as much memory from the NUMA node as we can, break the channel and ring allocations into individual allocations. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Re-issue interrupt if interrupt status not clearedLendacky, Thomas2017-06-291-2/+9
| | | | | | | | | | | | | | Some of the device interrupts should function as level interrupts. For some hardware configurations this requires setting some control bits so that if the interrupt status has not been cleared the interrupt should be reissued. Additionally, when using MSI or MSI-X interrupts, run the interrupt service routine as a tasklet so that the re-issuance of the interrupt is handled properly. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge tag 'pci-v4.11-changes' of ↵Linus Torvalds2017-02-231-5/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add ASPM L1 substate support - enable PCIe Extended Tags when supported - configure PCIe MPS settings on iProc, Versatile, X-Gene, and Xilinx - increase VPD access timeout - add ACS quirks for Intel Union Point, Qualcomm QDF2400 and QDF2432 - use new pci_irq_alloc_vectors() in more drivers - fix MSI affinity memory leak - remove unused MSI interfaces and update documentation - remove unused AER .link_reset() callback - avoid pci_lock / p->pi_lock deadlock seen with perf - serialize sysfs enable/disable num_vfs operations - move DesignWare IP from drivers/pci/host/ to drivers/pci/dwc/ and refactor so we can support both hosts and endpoints - add DT ECAM-like support for HiSilicon Hip06/Hip07 controllers - add Rockchip system power management support - add Thunder-X cn81xx and cn83xx support - add Exynos 5440 PCIe PHY support * tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (93 commits) PCI: dwc: Remove dependency of designware on CONFIG_PCI PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host PCI: dwc: Split pcie-designware.c into host and core files PCI: dwc: designware: Fix style errors in pcie-designware.c PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() PCI: dwc: all: Split struct pcie_port into host-only and core structures PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() PCI: dwc: all: Rename cfg_read/cfg_write to read/write PCI: dwc: all: Use platform_set_drvdata() to save private data PCI: dwc: designware: Move register defines to designware header file PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code PCI: dra7xx: Group PHY API invocations PCI: dra7xx: Enable MSI and legacy interrupts simultaneously PCI: dra7xx: Add support to force RC to work in GEN1 mode PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional() PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory PCI: exynos: Support the PHY generic framework Documentation: binding: Modify the exynos5440 PCIe binding phy: phy-exynos-pcie: Add support for Exynos PCIe PHY Documentation: samsung-phy: Add exynos-pcie-phy binding ...
| * amd-xgbe: Update PCI support to use new IRQ functionsTom Lendacky2017-01-131-5/+3
| | | | | | | | | | | | | | | | | | | | | | Some of the PCI MSI/MSI-X functions have been deprecated and it is recommended to use the new pci_alloc_irq_vectors() function. Convert the code over to use the new function. Also, modify the way in which the IRQs are requested - try for multiple MSI-X/MSI first, then a single MSI/legacy interrupt. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | amd-xgbe: Add a hardware quirk for register definitionsLendacky, Thomas2017-01-221-0/+2
|/ | | | | | | | | | A newer version of the hardware is using the same PCI ids for the network device but has altered register definitions for determining the window settings for the indirect PCS access. Add support to check for this hardware and if found use the new register values. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for a KR redriverLendacky, Thomas2016-11-131-0/+6
| | | | | | | | | | This patch provides support for the presence of a KR redriver chip in between the device PCS and an external PHY. When a redriver chip is present the device must perform clause 73 auto-negotiation in order to set the redriver chip for the downstream connection. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for MDIO attached PHYsLendacky, Thomas2016-11-131-0/+12
| | | | | | | | | Use the phylib support in the kernel to communicate with and control an MDIO attached PHY. Use the hardware's MDIO communication mechanism to communicate with the PHY. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for SFP+ modulesLendacky, Thomas2016-11-131-1/+14
| | | | | | | | | Add support for recognizing and using SFP+ modules directly. This includes using the I2C support to read and interpret the information returned from an SFP+ module and configuring things properly. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add I2C support for sideband communicationLendacky, Thomas2016-11-131-0/+64
| | | | | | | | | Add support to initialize and use the I2C controller within the hardware in order to perform sideband communication, e.g. determine the SFP media type that is installed. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add ECC status support for the device memoryLendacky, Thomas2016-11-131-1/+34
| | | | | | | | | Some versions of the amd-xgbe device are capable of reporting ECC error information back to the driver. Add support to process, track and report on this information. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for new DMA interrupt modeLendacky, Thomas2016-11-131-0/+5
| | | | | | | | | | | | | The current per channel DMA interrupt support is based on an edge triggered interrupt that is not maskable. This results in having to call the disable_irq/enable_irq functions in order to prevent interrupts during napi processing. The hardware now has a way to configure the per channel DMA interrupt that will allow for masking the interrupt which prevents calling disable_irq/enable_irq now. This patch makes use of this support. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add PCI device supportLendacky, Thomas2016-11-131-1/+38
| | | | | | | Add support for new PCI devices to the driver. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add a workaround for Tx timestamp issueLendacky, Thomas2016-11-131-0/+1
| | | | | | | | | | | | | | | Update the reading of the Tx timestamp to account for a hardware issue on how the fields and interrupt are cleared. The "seconds" portion of the timestamp should be read first, followed by the "nanoseconds" portion. Reading the "nanoseconds" portion should clear the timestamp data and the interrupt. Because of an issue with the hardware this order is reversed and reading the "seconds" portion actually clears the timestamp. The code currently follows this workaround, but to guard against future versions where this is fixed add a field to the version data to indicate if the workaround is required or not. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for supporting PCI devicesLendacky, Thomas2016-11-041-4/+19
| | | | | | | | | Update the driver framework to separate out platform/ACPI specific code from general code during device initialization. This will allow for the introduction of PCI device support. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Update how to determine DMA channel statusLendacky, Thomas2016-11-041-1/+1
| | | | | | | | | | Tx and Rx DMA channel status determiniation is different depending on the version of the hardware. Update the channel status processing code to account for the change. Also, reduce the timeout value used when stopping the channels. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Support for 64-bit management counter registersLendacky, Thomas2016-11-041-0/+1
| | | | | | | | | Add support for reading all management counter registers as 64-bit values. The indication of whether to read the high 32-bits to form a 64-bit value is indicated in the version data. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for a new PCS register access methodLendacky, Thomas2016-11-041-0/+9
| | | | | | | | | Prepare the code to be able to support accessing of the PCS registers in a new way, while maintaining the current access method. Provide a version specific field that indicates the method to use. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for clause 37 auto-negotiationLendacky, Thomas2016-11-041-1/+10
| | | | | | | Add support to be able to use clause 37 auto-negotiation. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for introduction of clause 37 autonegLendacky, Thomas2016-11-041-5/+9
| | | | | | | | | | | Prepare for the future introduction of clause 37 auto-negotiation by updating the current auto-negotiation related functions to identify them as clause 73 functions. Move interrupt enablement to the enable/disable auto-negotiation functions. Update what will be common routines to check for the current type of AN and process accordingly. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for working with more than one type of phyLendacky, Thomas2016-11-041-63/+67
| | | | | | | | | Prepare the code to be able to work with more than one type of phy by adding additional callable functions into the phy interface and removing phy specific settings/functions from non-phy related files. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Perform priority-based hardware FIFO allocationLendacky, Thomas2016-11-041-0/+26
| | | | | | | | | | Allocate the FIFO across the hardware Rx queues based on the priority of the queues. Giving more FIFO resources to queues with a higher priority. If PFC is active but not enabled for a queue, then less resources can allocated to the queue. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for priority-based FIFO allocationLendacky, Thomas2016-11-041-1/+2
| | | | | | | | | | | | | Currently, the Rx and Tx fifos are evenly allocated between the hardware queues of the device. As more queues are instantiated, the fifo memory needs to be able to be allocated based on queue priority. This allows for higher priority queues to have more fifo memory than lower priority queues. Prepare for this by modifying the current fifo calculation to assign the fifo queue allocation in an array that is then used to program the hardware. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* xgbe: constify get_netdev_ops and get_ethtool_opsstephen hemminger2016-08-311-2/+3
| | | | | | | | | | | Casting away const is bad practice. Since this is ARM specific driver don't have hardware actually test this. Having getter functions for ops is really unnecessary code bloat, but not going to touch that. Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Mask auto-negotiation interrupts in ISRLendacky, Thomas2016-02-171-2/+3
| | | | | | | | | | | | | | Currently the auto-negotiation interrupt handling disables the irq instead of masking off the interrupts. This was done because the phy library was originally used to read and write the PCS registers, which could not be performed in interrupt context. Now that the phy library is no longer used to read and write the PCS registers the interrupts can be masked off in the interrupt service routine eliminating the need to call disable_irq/enable_irq. This also requires changing the protection mutex to a spinlock. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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